Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-17
Configuration Registers
17:16 RW 1h
TWR: Write to Read Delay
The minimum delay from the Write command to the next Read command on
the same branch DDR channel.This parameter is varied to avoid data strobe
protocol violations on the DIMM data bus. Table 3-5 defines the settings of this
parameter as a function of DMH parameters.
0 0 10 ns
0 1 20 ns
1 0 30 ns
1 1 40 ns
15 RW 0
RWAC: Read or Write during Write Access Period
This bit may be set if all the DRAM controlled by the SNC can perform
concurrent auto-precharge operations to different banks. If 0, the maximum
rate of auto-precharge writes to a DIMM will be one write every 50ns. The
MC.RROE bit should be set to limit reads and writes during read access
periods.
0 Some DIMMs do not support reads or writes during write access period.
1 All DIMMs support reads or writes during write access period.
14 RV 0 Reserved
13:12 RW 2h
TRR: Read to Read Delay
The minimum delay from one Read command to another Read command on a
channel. MC.RROE determines whether this applies to all reads on a channel
or just reads to a different DIMM on the same channel. This parameter is
varied to avoid data strobe protocol violations on the DIMM data bus.
0 0 Reserved.
0 1 Reserved.
1 0 30 ns
1 1 40 ns (Supported only for memory initialization)
11:10 RW 1h
TWW: Write to Write Delay
The minimum delay from the Write command to the next Write command on
the same branch DDR channel.
0 0 Reserved.
0 1 20 ns
1 0 30 ns (Supported only for memory initialization)
1 1 40 ns
9:8 RW 0
TRCD: Ras to Cas Delay
The minimum delay from the RAS to a subsequent CAS to the same DIMM
Row. This parameter is programmed according to the highest
tRCD and tRAP
parameters of the DDR DIMMs present.
0 0 20 ns (
tRCD= tRAP)
0 1 30 ns (
tRCD< tRAP)
1 0 Reserved.
1 1 Reserved.
7:6 RW 0
TRA: Read to Activate Delay
The minimum delay from the Read command to the next ACT command to the
same bank. This parameter is programmed according to the timing calculation:
t
RAS + tRP - tRCD. Refer to DDR AC Characteristics specification for the timing
parameters in the calculations.
0 0 50 ns
0 1 60 ns
1 0 Reserved
1 1 Reserved
Device: NodeID
Function: 1
Offset: C0h (Continued)
Bit Attr Default Description