Datasheet

Configuration Registers
3-18 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Table 3-5 defines the legal combinations for TRW, TWR as a function of DIMM data bus timing
parameters configured in the DMH. There may be a small variation across DMHs and across the
DIMMs on each DMH in the sum of t
CL
+ t
DPL
+ t
DSD
. The maximum must be used.
Note: t
CL
is the DIMM CAS Latency. t
DPL
is the DIMM Path Latency, and t
DSD
is DIMM Strobe Offset.
3.7.4 DRC: DRAM Maintenance Control Register
The Refresh Value field specifies the number of cycles (nominally 5ns) between refreshes. Since
refreshes are generated for all 16 supported DIMM sides, the refresh interval for any given DIMM
is 16 times as long as the Refresh Value field. A value of 195 sets the DIMM refresh interval to the
standard value of 15.6 us.
5:4 RW 2h
TWA: Write to Activate Delay
The minimum delay from the Read command to the next ACT command to the
same bank. This parameter is programmed according to the DIMM timing
parameters:
tWR + tRP + 30ns
Refer to DDR AC Characteristics specification for the timing parameters in the
calculations.
0 0 50 ns
0 1 60 ns
1 0 70 ns
1 1 Reserved
3:1 RW 1h
TRFC: Auto Refresh to Act Delay
The minimum delay from the Auto Refresh command to the next ACT
command to the same device. This parameter is set to the largest
tRFC of the
DIMMs present.
0 0 0 70 ns
0 0 1 80 ns
0 1 0 90 ns
0 1 1 100 ns
1 0 0 120 ns
1 0 1 130 ns
1 1 0 140 ns
1 1 1 160 ns
0RW1h
TRC: Act to Act Delay
The minimum delay from the Act command to the next ACT command to the
same device. This parameter is programmed according to the largest
tRRD of
the DIMMs present.
0 10 ns
1 20 ns
Device: NodeID
Function: 1
Offset: C0h (Continued)
Bit Attr Default Description
Table 3-5. Legal Combinations of TRW, TWR
DMH Maximum
t
CL
+ t
DPL
+ t
DSD
TRW
(STM[19:18])
TWR
(STM[17:16])
15-17.5ns (6-7 Rclks) 01 10
20-25ns (8-11 Rclks) 10 01
27.5-35ns (12-15 Rclks) 11 00