Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-19
Configuration Registers
A value of 0 indicates that refreshes should not be generated. For more information on refresh see
Section 5.3.4, “DDR Maintenance Operations.”
3.7.5 RCD: RAMBUS* Configuration Data Register
This register is used with the SCC register to access DMH registers or serial presence detect
information. This register is written for write data and holds the result of any operation specified by
the SCC register. Each operation is shifted out the serial interfaces for each RAMBUS
concurrently. There is one 16-bit field in this register for the data to/from each RAMBUS.
3.7.6 SCC: DDR SDRAM Configuration Command Register
This register is used with the RCD register to access DDR SDRAM and DMH control registers or
serial presence detect information. The SCC specifies the command to be executed. Writing this
register causes transactions on the RAMBUS serial control bus which may be translated by
expanders into serial presence detect transactions. The data for operations comes from, or is
returned to the RCD register. The frequency of SCLK never exceeds 1MHz.
Device: NodeID
Function: 1
Offset: 46h
Bit Attr Default Description
15:12 RV 0 Reserved
11:0 RW 0
Refresh Value
For DDR, the number of cycles between refreshes. For testing purposes, this
field may be set from 0 to 50.
Device: NodeID
Function: 1
Offset: 48h
Bit Attr Default Description
63:48 RW 0 R3D: RAMBUS 3 data.
47:32 RW 0 R2D: RAMBUS 2 data.
31:16 RW 0 R1D: RAMBUS 1 data.
15:0 RW 0 R0D: RAMBUS 0 data.
Device: NodeID
Function: 1
Offset: 54h
Bit Attr Default Description
31:30 RV 0 Reserved
29 RW 0
MOE: Maintenance Operation Enable
When set, the SNC issues maintenance operations such as refresh,
temperature calibration, etc. This bit defaults to 0 so that these operations will
not interfere with initialization operations controlled by this register. When
memory initialization is complete, software must set this bit. It may be up to
100 ms before this bit takes effect.