Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheetv
3.10.11 FSBPMEU[1:0]: Processor Bus Perform Monitor
Utilization Events.................................................................................3-55
3.10.12 SPPMD[1:0]: SP Performance Monitor Data.......................................3-57
3.10.13 SPPMC[1:0]: SP Performance Compare ............................................3-57
3.10.14 SPPMR[1:0]: SP Performance Monitor Response ..............................3-58
3.10.15 SPPME[1:0]: SP Performance Monitor Events ...................................3-60
3.10.16 HPPMR: Hot Page Control and Response..........................................3-61
3.10.17 HPADDR: Hot Page Index ..................................................................3-63
3.10.18 HPDATA: Hot Page Data ....................................................................3-63
3.10.19 HPCMP: Hot Page Count Compare....................................................3-63
3.10.20 HPBASE: Hot Page Range Base........................................................3-64
3.10.21 HPMAX: Hot Page Max Range Address.............................................3-64
3.10.22 HPRCTR: Hot Page Range Counter...................................................3-65
4 System Address Map ......................................................................................................4-1
4.1 Memory Map ......................................................................................................4-1
4.1.1 Compatibility Region .............................................................................4-2
4.1.2 System Region ......................................................................................4-3
4.1.3 High and Low Memory Mapped I/O (MMIO) .........................................4-7
4.1.4 Memory Mapped Configuration Space..................................................4-8
4.1.5 Main Memory Region ............................................................................4-8
4.2 Memory Address Disposition............................................................................4-12
4.2.1 Registers Used for Address Routing...................................................4-12
4.2.2 Inbound Transactions to SIOH............................................................4-16
4.2.3 Local/Remote Decoding for Requests to Main Memory......................4-18
4.2.4 Default SP Requirement in Single Node .............................................4-18
4.3 I/O Address Map ..............................................................................................4-18
4.3.1 Special I/O addresses .........................................................................4-18
4.3.2 Outbound I/O Access ..........................................................................4-19
4.3.3 Inbound I/Os........................................................................................4-20
4.4 Configuration Space.........................................................................................4-20
4.5 Illegal Addresses..............................................................................................4-21
4.5.1 Master Abort........................................................................................4-21
4.5.2 Processor Requests............................................................................4-21
4.5.3 Scalability Port Requests ....................................................................4-21
5 Memory Subsystem.........................................................................................................5-1
5.1 Memory Controller Operation.............................................................................5-1
5.1.1 Memory Arbitration................................................................................5-1
5.1.2 Reads....................................................................................................5-2
5.1.3 Writes ....................................................................................................5-3
5.2 Error Correction..................................................................................................5-4
5.2.1 Scrub Address Generation....................................................................5-4
5.2.2 Correction for System Accesses ...........................................................5-5
5.2.3 Software Scrubs....................................................................................5-5
5.2.4 Memory Error Correction Code .............................................................5-5
5.2.5 Memory Device Failure Correction and Failure Isolation ......................5-8
5.2.6 Memory Test .........................................................................................5-8
5.3 DDR Organization ..............................................................................................5-9
5.3.1 DDR Configuration Rules......................................................................5-9
5.3.2 DDR Features Supported....................................................................5-10
5.3.3 Power Management ............................................................................5-14
5.3.4 DDR Maintenance Operations ............................................................5-15