Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-21
Configuration Registers
3.7.7 MTS: Memory Test and Scrub Register
This register is used to control an engine that initializes, tests, and corrects errors in memory.
Table 3-6. DDR IOP Decodes
Operation Name Details
DMH Register Read
The serial read of the DMH register specified by the MRA field. The data read will be
available in RCD register when IIO bit is cleared by hardware to 0.
DMH Register Write
The serial write of the DMH register specified by the MRA field. The write data is
provided in the RCD register.
DMH SIO Reset
A SIO pin initialization sequence is sent to the DMH. When this operation occurs, the
DMH serial interface is reset. This does not affect DMH configuration.
Serial Presence
Detect Write
Initiate a SPD register write via the serial I/O to the DMH. This will cause an SPD
operation to the DIMM specified by the DIMM field. The SNC also issues an SPD
write on the SMBus. The MRA field specifies the byte addressed.
Serial Presence
Detect Read
Initiate a SPD register read via the serial I/O to the DMH. This will cause an SPD
operation to the DIMM specified by the DIMM field. The SNC also issues an SPD
write on the SMBus. The MRA field specifies the byte addressed.
SNC RAC Manual
Current Calibration
Loads all four RAC Current Control Registers with the values in the RCD register.
Load SNC RAC[n]
Configuration Register
Loads the least significant 32 bits in the RCD register into the RAC config register
within RAC[n]. n may be one of 0, 1, 2, 3.
SNC RAC Initialize
Initiate Power-up sequence, Current Calibration, and Temperature Calibration of
SNC RACS. This sequence takes about 250us. This operation will only be executed
once after each PWRGOOD deassertion. Subsequent RAC initialize operations will
have no effect other than to set the IIO flag to indicate completion.
SNC RAC Auto
Current Calibration
Initiate the Automatic Current Control Sequence defined by RAMBUS.
SNC RAC Thermal
Calibration
Perform Slew Rate operation defined by RAMBUS.
DMH Time Synch Send a Time Synchronization packet to the DMH.
Device: NodeID
Function: 1
Offset: 58h
Bit Attr Default Description
31 RV 0 Reserved
30 RW 0
Validation Mode
0 = Counter increments by 1.
1 = For validation purposes, counter increments by 128 MB.
29 RW 0
Scrub Enable
0 = Test mode: When the Go bit is set, the engine performs the block copies
described in Section 5.2.6, “Memory Test.”
1 = Thirty-two data buffers are reserved for memory test.
1 = Scrub mode: the engine will continuously read then write each address
described by the MIR registers. See Section 5.2, “Error Correction.”