Datasheet

Configuration Registers
3-22 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.7.8 XTPR[7:0]: External Task Priority Register
These registers define the redirectable interrupt priority for APIC agents on the node. The contents
of these registers are modified by the xTPR_Update transaction on the processor bus. Index into
the XTPR registers is defined by Ab[23:21]#. These registers are used for lowest priority delivery
through interrupt redirection by the chipset. Whenever this register is updated, the Logical
Submode bit in the FSBC register is also updated.
28 RW 0
Go
Used only in test mode.
When set, initiates the test. When the test is complete, the SNC will reset this
bit. This bit can therefore be polled to determine when the test is complete.
Writing a 1 to this bit while it is already set will have no effect. Writing a 0 to this
bit will have no effect.
27:25 RW 0
Reduce Test Range
This field is used for validation. It must be set to 000 in scrub mode.
000 Test entire range defined by MIR
100 Test only the lowest 512K defined by the MIR
010 Test only the lowest 64K defined by the MIR
001 Test only the lowest 16K defined by the MIR
24:4 RV 0 Reserved
3:0 RW 0
MIRNUML
Identifies the index of the Memory Interleave Range to be tested. See
Section 3.6.9, “MIR[9:0]: Memory Interleave Range Registers.”
Device: NodeID
Function: 1
Offset: 58h (Continued)
Bit Attr Default Description
Device: NodeID
Function: 0
Offset: 0:A4h,1:A8h,2:ACh,3:B0h,4:B4h,5:B8h,6:BCh,7:C0h
Bit Attr Default Description
31:8 RV 0 Reserved
7RW0
EN: TPR Enable
This bit reflects the value of Ab[31]#. When Ab[31]# is asserted, the value of
this bit will be 0.
6:4 RV 0 Reserved
3:0 RW 0
TPR: Task Priority
The processor with the lowest enabled value will be assigned the re-directable
interrupt. This field is updated with Ab[30:27]# of the xTPR_Update
transaction.