Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-23
Configuration Registers
3.8 Reset, Boot and Control Registers
3.8.1 SYRE: System Reset
This register controls SNC reset behavior. Any resets produced by a write to this register must be
delayed until the configuration write is completed on the initiating interface (SP, processor bus,
SMBus, JTAG).
3.8.2 CVDR: Configuration Values Driven on Reset
The SNC drives the contents of this register on A[31:3]# whenever it asserts RESET# due to hard
reset deassertion. These values are driven during RESET# assertion, and for two host clocks past
the trailing edge of RESET#. The bit numbers in this register correspond to the index of the address
bit driven. For example, if CVDR[10] is set, A[10]# will be asserted.
Device: NodeID
Function: 0
Offset: 40h
Bit Attr Default Description
15:14 RV 0 Reserved
13 RW* 0
SAVCFG: Preserve Configuration
When this bit is set, SNC configuration register contents (except for this bit and
SAVMEM) are not cleared by hard reset. As this bit is cleared by reset,
software must set it after each reset if this behavior is desired for the next
reset. If this bit is set, BOFL will not be cleared by reset. Software should use
the Boot Flag Reset bit to re-enable the BOFL mechanism.
12 RW* 0
SAVMEM: Preserve Memory
This bit must not be set unless the SCC.MOE is set to enable the memory
operation timers. Otherwise, the SNC will not complete its reset procedure,
and a PWRGOOD pulse will be required to recover.
When this bit is set, memory contents are preserved through hard reset. The
registers in Section 3.7, “Memory Controller Registers” retain their values
through reset. As this bit is cleared by reset, software must set it after each
reset if this behavior is desired for the next reset.
This bit should not be set unless the SCC.MOE bit is set to enable memory
maintenance operations.
11 RW* 0
Boot Flag Reset
When this bit is set, the boot flag register (BOFL) is returned to its default
value. The SNC will clear this bit once this action is complete.
10 RW* 0
SNC Reset
The rising edge on this bit will initiate the Hard Reset sequence. The SNC will
clear this bit once Hard Reset is asserted.
9RW*0
Node Soft Reset
The rising edge on this bit will lead to the assertion of the INIT# pin for four
cycles. The SNC will clear this bit once this action is complete.
8RW*0
System Hard Reset
The rising edge on this bit will lead to the assertion of the RESETO# pin.
Depending on system reset routing, this reset can be used to reset just the
local node, or the entire system. The SNC will clear this bit once this action is
complete. The timing of this RESETO# assertion should not be affected by
Hard Reset.
7:0 RV 0 Reserved