Datasheet

Configuration Registers
3-24 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
This register is sticky through reset; that is, the contents of the register remain unchanged during
and following a Hard Reset. This allows system configuration software to modify the default
values and reset the system to pass those values to all host bus devices. The default values shown
above represent the state of the register following a power-good reset.
The CVDR bits do not affect SNC operation except for driving A[31:3]#. In order to enable
external system logic to override the values driven by the SNC, the values captured from A[31:3]#
affect SNC operation.
Device: NodeID
Function: 0
Offset: 44h
Bit Attr Default Description
31:28 RWS 0
SNC: CPU Kill
When set, these bits disable the corresponding processor so that the
remainder of the machine may be rebooted. The Agent numbers are those
established by BR[0]# rotation. In systems that use on die termination for the
processor bus, the CPU providing the termination should not be disabled. It is
permissible to set the CPU Kill bits when the corresponding processor is not
present so that the corresponding bits in the CVCR register reflect the number
of working processors on the node. The Itanium 2 processor uses Agent[2:1].
A[31]# Tristate Agent 6,7
A[30]# Tristate Agent 4,5
A[29]# Tristate Agent 2,3
A[28]# Tristate Agent 0,1
27:22
RWS
/RV
0
A[27:22]# Value
The use of these address bits during reset is reserved by the processor.
21:17 RWS 0
Processor Core to Bus Clock Ratio
A[21:17]# define the bus to core clock ratio for the Itanium 2 processor.
16 RV 0 Reserved
15 RWS 0
Request Bus Parking Enable
If A[15]# is set, Itanium 2 processors may park on the system bus. This should
not be set if FSBC.ASOEN is set.
14:13
RWS
/RV
0
Drive A[14:13]#
The use of these address bits during reset is reserved.
12:11 RWS 0
APIC Cluster ID
This value is driven on A[12:11]#. It is easier for firmware to directly configure
the APIC ID register than to set these bits and reset.
10 RWS 0
Enable BINIT# Observation
If set A[10]# will be asserted and All host bus agents will enable BINIT#
observation logic.
9RWS0
Enable BERR# Input
If set, A[9]# will be asserted and all host bus agents will enable BERR#
observation by the processors.
8RWS0
Drive A[8]#
If set, A[8]# will be asserted.
7RWS0
In-order Queue Depth 1
If set, A[7]# will be asserted, and all agents on the host bus will limit their In-
Order Queue Depth to 1.
6RWS0
1 MEG Power-on Reset Vector
If set, A[6]# will be asserted, and all agents on the host bus will begin fetching
code below 1MB (000F_FFF0h) instead of below 4GB (00_FFFF_FFF0h).