Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-25
Configuration Registers
3.8.3 CVCR: Configuration Values Captured on Reset
This register holds the values of A[31:3]# sampled. The sampled values are driven by the SNC
according to the CVDR
register. Whereas the CVDR register only affects the pins driven at reset,
SNC operation is affected by some of the sampled values. The default values shown above
represent the state of the register following a power-good reset.
5:4
RWS
/RV
0
Drive A[5:4]#
The use of these address bits during reset is reserved by the processor.
3
RWS
/RV
0
Drive A[3]#
The use of these address bits during reset is reserved by the processor.
2:0 RV 0
Drive A[34:32]#
The use of these address bits during reset is reserved by the processor.
Device: NodeID
Function: 0
Offset: 44h (Continued)
Bit Attr Default Description
Device: NodeID
Function: 0
Offset: 48h
Bit Attr Default Description
31:28 RO 0
CPU Kill
Captured from the A[31:28]# pins. When set, these bits indicate that the
corresponding CPU has been disabled since the last reset. Software may use
these bits to determine the number of working processors on the node.
A[31]# Tristate Agent 6,7
A[30]# Tristate Agent 4,5
A[29]# Tristate Agent 2,3
A[28]# Tristate Agent 0,1
27:22 RV 0
A[27:22]# Value
Captured from A[27:22]#. The use of these address bits during reset is
reserved.
21:16 RO 0
Processor Core to Bus Clock Ratio
This field is set to the values of A#[21:16] sampled on RESET#.
Bits 21:17 define the bus to core clock ratio for the Itanium 2 processor. Bit 16
should not be set in the Itanium 2 processor-based systems.
SNC operation is not affected by this field.
The default value of 0 will select the lowest clock frequency so that any speed
processor will be able to execute following PWRGD reset.
15 RO 0
Request Bus Parking Enable
Captured from A[15]#. This bit, when set, indicates that the Itanium 2
processors will park on the system bus. This bit should not be set if the
FSBC.ASOEN is set. SNC operation is not affected by this bit.
14:13 RO 0
A[14:13]# Value
Captured from A[14:13]#. The use of these address bits during reset is
reserved by the processor. SNC operation is not affected by this bit.
12:11 RO 0
APIC Cluster ID
Captured from A[12:11]#. This field represents the APIC Cluster identifier.
10 RO 0
Enable BINIT# Input
Captured from A[10]#. If set, the SNC will enable BINIT# logic.