Datasheet

vi Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
6 Reliability, Availability, and Serviceability........................................................................6-1
6.1 Data Integrity......................................................................................................6-1
6.1.1 End-to-end Error Correction..................................................................6-5
6.1.2 Data Poisoning......................................................................................6-6
6.1.3 Error Reporting......................................................................................6-6
6.1.4 Interface Details ....................................................................................6-7
6.1.5 Time-Out ...............................................................................................6-8
6.2 RAS: System Components Roles and Responsibilities .....................................6-9
6.2.1 Machine Check Architecture (MCA)......................................................6-9
6.2.2 Server Management (SM)...................................................................6-10
6.2.3 OS/System Software...........................................................................6-10
6.2.4 Device Driver.......................................................................................6-10
6.2.5 Summary.............................................................................................6-11
6.3 Availability ........................................................................................................6-11
6.4 Hot-Plug ...........................................................................................................6-12
6.4.1 Hot-Plug Support on SP......................................................................6-12
6.5 Chipset Error Record .......................................................................................6-13
6.5.1 Generating the Error Record...............................................................6-13
6.5.2 Chipset Record Section ......................................................................6-13
6.5.3 Error Interpretation Guidelines ............................................................6-15
6.5.4 ESP Error Logs ...................................................................................6-20
7 Clocking ..........................................................................................................................7-1
7.1 System Clocking ................................................................................................7-1
7.2 Clock Gearing and Fractional Ratios .................................................................7-1
7.3 Master Clock ......................................................................................................7-1
7.4 Itanium
®
2 Processor Bus Clock........................................................................7-3
7.4.1 Differential Reference Clock (BUSCLK & BUSCLK#)...........................7-3
7.5 RAC Clocking Support .......................................................................................7-3
7.6 DDR SDRAM Clocking Support.........................................................................7-4
7.7 Firmware Hub Clocking......................................................................................7-4
7.8 JTAG..................................................................................................................7-5
7.9 SMBus Clocking.................................................................................................7-5
7.10 Other Functional and Electrical Requirements...................................................7-5
7.10.1 Spread Spectrum Support.....................................................................7-5
7.10.2 PLL Lock Time .....................................................................................7-5
7.11 Analog Power Supply Pins.................................................................................7-5
8 System Reset..................................................................................................................8-1
8.1 Reset Types.......................................................................................................8-1
8.2 Reset Sequences...............................................................................................8-2
8.2.1 Power-up Reset Sequence ...................................................................8-3
8.2.2 Hard Reset............................................................................................8-7
8.2.3 Soft Reset ...........................................................................................8-12
8.2.4 Software initialization ..........................................................................8-12
8.2.5 Memory after Hard Reset....................................................................8-12
8.3 Reset Signals...................................................................................................8-12
8.3.1 ICH4: PWROK ....................................................................................8-13
8.3.2 Basic Reset Distribution......................................................................8-13
8.3.3 SIOH: DET ..........................................................................................8-13
8.3.4 ICH4: PCIRST#...................................................................................8-13
8.3.5 SNC and SIOH and SPS: RESETI#....................................................8-14
8.3.6 SIOH: RESET66# ...............................................................................8-15