Datasheet

Configuration Registers
3-30 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.8.11 SNCINCO: SNC Interface Control
This register controls all the physical interfaces of the chip except SP.
15:12 RW 0
IDSEL for D8 Range
IDSEL for the local firmware address range FFD8_0000h - FFDF_FFFFh.
11:8 RW 0
IDSEL for D0 Range
IDSEL for the local firmware address range FFD0_0000h - FFD7_FFFFh.
7:4 RW 0
IDSEL for C8 Range
IDSEL for the local firmware address range FFC8_0000h - FFCF_FFFFh.
3:0 RW 0
IDSEL for C0 Range
IDSEL for the local firmware address range FFC0_0000h - FFC7_FFFFh.
Device: NodeID
Function: 0
Offset: 70h (Continued)
Bit Attr Default Description
Device: NodeID
Function: 0
Offset: 6Ah
Bit Attr Default Description
15:8 RV 0 Reserved
7RW0
Default SP
All SNCs must have the same default switch network
This bit affects SP request routing.
SP0 is selected.
SP1 is selected.
6RV0 Reserved
5RWS0
Disable Processor Bus Interface
When set, this bit will tri-state all processor bus outputs and mask all inputs.
Any snoop requests required by the SP should return clean responses.
4RO0
LPCSEL
Allows software to inspect the state of the LPCSEL strap pin.This strap pin
defines the protocol of devices on the LPC/FWH interface.
Use FWH protocol to access the flash devices.
Use LPC protocol to access the flash devices.
3:2 RV 1
LPC Clock Ratio
Those bits determines the clock divide ratio of central clock vs. LPC clock. The
initial central clock is assumed to be 200 MHz.
Note: Writing this field has no effect. Only the 6:1 encoding is supported.
1RWS0
LPCDIS: Disable LPC Interface
Allows software to disable LPC/FWH interface. Table 3-7 defines the effect of
this bit on the LPC/FWH interface.
0RO0
LPCENPIN: LPC Strap Disable
Allows software to inspect the state of the LPCEN strap pin. The polarity of this
bit is inverted relative to the pin. Table 3-7 defines the effect of this bit on the
LPC/FWH interface.