Datasheet
Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-31
Configuration Registers
3.8.12 SP0INCO, SP1INCO: SP Interface Control
These registers are common across all E8870 chipset components, and they provide the control and
status for each SP. Associated with each SP are two GPIO pins (GPIO[1:0]). These pins are open
drain, and are observable and controllable from this register.
The SNC uses the Enable_SP field to override internal assignment of transactions to ports. A
transaction targeted toward one SP will be re-routed to the other SP if the targeted SP is disabled. If
neither of the SPs are enabled, all transactions sent to SP’s are master-aborted.
Table 3-7. Enabling the LPC/FWH Interface
LPCEN Pin
SNCINCO Bit[0]:
LPCENPIN
SNCINCO Bit[1]:
LPCDIS
LPC
011
Tri-state all LPC outputs and mask all
inputs. All LPC traffic (accesses to
BIOS/PAL/SAL and FWH feature space)
are routed to the SP.
010
101
1 0 0 LPC/FWH is enabled.
Device: NodeID
Function:2 for SP0INCO, 3 for SP1INCO
Offset: C0h
Bit Attr Default Description
31:26 RWS 0
Scratch Bits
These bits may be used by software to record information specific to this
SP. For example, hot-plug sequencing history.
25 RO GPIO1
GPIO1 STATE
This bit is used to monitor the state of the SPGPIO1 pin.
0 = GPIO1 pin is high (inactive)
1 = GPIO1 pin is low (active)
24 RO GPIO0
GPIO0 STATE
This bit is used to monitor the state of the SPGPIO0 pin.
0 = GPIO0 pin is high (inactive)
1 = GPIO0 pin is low (active)
23 RWS 0
GPIO1 EN
This bit is used to control the state of the SPGPIO1 pin.
0 = Do not drive the GPIO1 pin (input only)
1 = Drive the GPIO1 pin low (open drain output)
22 RWS 0
GPIO0 EN
This bit is used to control the state of the SPGPIO0 pin.
0 = Do not drive the GPIO0 pin (input only)
1 = Drive the GPIO0 pin low (open drain output)
21 RW 0
INT_OUT
0 = This port does not drive the INT_OUT# pin low.
1 = Drive the INT_OUT# pin low (open drain output)
20:19 RO 0
SPAlign
The value of this field reflects the staging delays through the scalability port
input mux to frame the transfer of data from the SP source synchronous
data transfer to the core clock of the component.