Datasheet

Configuration Registers
3-32 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
18:16 RWS 101
Response Credits
Credits supported by this SP port on the response VC. Credit = 2
size
except
that when size >= 101, credit = 25 instead of 32. These bits are sent in the
idle flits. Must be set to a value <= to 25 for reliable SP operation.
15:13 RWS 101
Request Credits
Credit supported by this SP port on request VC. Credit = 2
size
except that
when size >= 101, credit = 25 instead of 32. These bits are sent in the idle
flits. Must be set to a value <= 25 for reliable SP operation.
12 RW 0
Disable SP Link Level Retry (LLR)
When set, this bit will disable link level retry on SP.
Note: SP LLR is always disabled during framing/initialization.
11:9 RO 0
Connecting SP Response Credits
Credits supported by the response VC of the device connected to this SP
port. Credit = 2
size
except that when size= 101, credit = 25 instead of 32.
This field is captured and updated from the idle flits.
8:6 RO 0
Connecting SP Request Credits
Credits supported by the request VC of the device connected to this SP
port. Credit = 2
size
except that when size = 101, credit = 25 instead of 32.
This field is captured and updated from the idle flits.
5RW
!LPCEN OR’ed
!CPUPRES
Pins
Enable SP
0 = The port is disabled. The outputs of the SP excluding SPSync are tri-
stated. Deassertion will cause the port to deassert SPSync and enter
initialization sequence. Disabling an SP should not be done with a
configuration transaction from the same SP as the one being disabled.
The configuration write will not complete.
1 = Enable SP output drivers. The port must complete initialization and
framing before data can be transferred.
4RO0
Idle Flit Acknowledgment Detected
Detected idle_ack from the idle flits received by this SP. This bit is cleared
at the beginning of the initialization sequence.
3RO0
Idle Flit Detected
Set during framing when 256 valid idle flits in a row are detected by the SP
receiver. This bit is cleared at the beginning of the initialization sequence.
2RW0
Interrupt on SP Idle Flit State Change
1 = A 0->1 transition of the Idle-flit-detected bit in the above field will
trigger an interrupt from this chip via INT_OUT#.
0 = Deassert the interrupt request controlled by this bit. The open drain
interrupt pin (INT_OUT#) may remain asserted if other interrupt
conditions exist.
Note: The detection mechanism is initialized at the start of port framing
only.
1 RO SP_PRES
SP_PRES State
This bit follows the SP_PRES pin associated with this SP. When
deasserted, the output of the SP are tri-stated, and transactions targeting
the SP are master-aborted.
0RW0
Interrupt on Pin SP_PRES State Change
1 = A 0->1 or 1->0 transition in the above field will trigger an interrupt from
this chip (via INT_OUT#).
0 = Deassert the interrupt request controlled by this bit. The open drain
interrupt pin (INT_OUT#) may remain asserted if other interrupt
conditions exist.
Device: NodeID
Function:2 for SP0INCO, 3 for SP1INCO
Offset: C0h (Continued)
Bit Attr Default Description