Datasheet

Configuration Registers
3-34 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Device: NodeID
Function: 2
Offset: 80h(31:0), 84h(63:32), 88h(96:64)
Bit Attr Default
ERR
Type
Description
95 ROS 0 N/A
Last ERR[2]# Value
If set, the ERR[2]# was asserted for four cycles before the SNC drives
ERR[2]# for the first fatal error. This implies that some other
component drove ERR[2]# first.
If this bit is clear, but set in all other components, this component
drove ERR#[2] first.
When all fatal bits are cleared in this register, ERR[2]# sampling is re-
enabled.
This bit does not get cleared automatically, but is cleared by writing a
“1” to it.
94 ROS 0 N/A
Last ERR[1]# Value
If set, the ERR[1]# pin was asserted for four cycles before the SNC
drives ERR[1]# for the first non-fatal error. This implies that some
other component drove ERR[1]# first.
If this bit is clear, but set in all other components, this component
drove ERR[1]# first.
When all uncorrectable bits are cleared in this register, ERR[1]#
sampling is re-enabled.
This bit does not get cleared automatically, but is cleared by writing a
“1” to it.
93 ROS 0 N/A
Last ERR[0]# Value
If set, the ERR[0]# pin was asserted for four cycles before the SNC
drives ERR[0]# for the first non-fatal error. This implies that some
other component drove ERR[0]# first.
If this bit is clear, but set in all other components, this component
drove ERR[0]# first.
When all correctable bits are cleared in this register, ERR[0]#
sampling is re-enabled.
This bit does not get cleared automatically, but is cleared by writing a
“1” to it.
Processor Bus Errors
92 RCS 0 Fatal F1: Illegal or Unsupported Transaction
91 RCS 0 Fatal
F2: Bus Protocol Error
Set if the SNC observes HITM on explicit write-back.
90 RCS 0 Fatal
F3: BINIT# Observed
Set when the signal is asserted by any bus agent.
89 RCS 0 Fatal
F4: System Bus Address Parity Error
The address may be corrupted, but if the request is without error, the
SNC will complete the request.
88 RCS 0 Fatal F5:Bus Request Parity Error
87 RCS 0 Unc
F6:Outbound Multi-Bit ECC Error
Outbound Multi-Bit ECC Error on FWH write
The SNC will generate poisoned ECC and forward to the SP, memory,
or FWH bus. Section 6.1.1, “End-to-end Error Correction” describes
the action taken at these interfaces.
86 RV 0 Unc Reserved