Datasheet

Configuration Registers
3-38 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.9.3 SERRST: Second Error Status
This register is used to report subsequent fatal and non-fatal errors. Multiple bits can be set in this
register. This register has the same format as register FERRST.
3.9.4 ERRMASK: ERRST MASK
The bit assignments of this register matches the format of FERRST register. Each bit in this register
will mask the corresponding bit in FERRST and SERRST. “Mask” here means that while the
corresponding bit in FERRST or SERRST register can still be set or cleared, but does not trigger
assertions on ERR pins. The default value is set so that no error is signalled after reset. This
prevents a cycle in which an error detected before this register can be written causes system logic
to assert RESETI#, restarting the sequence that caused the error which causes RESETI#.
Configuration Access Errors
1 RCS 0 Fatal
C1: Multi-Bit Data ECC Error on Configuration Write
The SNC will complete the configuration write on all interfaces, but not
perform the register write.
0RCS0Corr
C2: Single-Bit Data ECC Error on Configuration Write
The SNC will correct the error and perform the register write.
Device: NodeID
Function: 2
Offset: 80h(31:0), 84h(63:32), 88h(96:64) (Continued)
Bit Attr Default
ERR
Type
Description
Device: NodeID
Function: 2
Offset:8Ch(31:0), 90h(63:32), 94h(95:64)
Bit Attr Default Description
95:93 RV 0 Reserved
92:78 RCS 0 See register FERRST for the definition of each bit.
77:40 RV 0 Reserved
39:32 RCS 0 See register FERRST for the definition of each bit.
31:24 RV 0 Reserved
23:16 RCS 0 See register FERRST for the definition of each bit.
15:10 RV 0 Reserved
9:0 RCS 0 See register FERRST for the definition of each bit.
Device: NodeID
Function: 2
Offset:98h(31:0), 9Ch(63:32), A0h(71:64)
Bit Attr Default Description
95:93 RV 0 Reserved
92:78 RW 1
0 = no effect.
1 = mask the corresponding bit in FERRST and SERRST.