Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-39
Configuration Registers
3.9.5 RECFSB: Recoverable Error Control Information of
Processor Bus
This register latches control information in the response phase of the first non-fatal processor bus
error detected by the SNC. For LPC time-out errors, only the address, write, and read fields will be
logged. The contents of this register is only valid when one of the errors that set this register is
logged in the FERRST register.
77:40 RV 0 Reserved
39:32 RW 1
0 = no effect.
1 = mask the corresponding bit in FERRST and SERRST.
31:21 RV 0 Reserved
20:16 RW 1
0 = no effect.
1 = mask the corresponding bit in FERRST and SERRST.
15:10 RV 0 Reserved
9:0 RW 1
0 = no effect.
1 = mask the corresponding bit in FERRST and SERRST.
Device: NodeID
Function: 2
Offset:98h(31:0), 9Ch(63:32), A0h(71:64) (Continued)
Bit Attr Default Description
Device: NodeID
Function: 0
Offset: CCh(31:0), D0h(63:32), D4h(95:64)
Bit Attr Default Description
95:77 RV 0 Reserved
76 ROS 0 SNC initiated this transaction
75 ROS 0 Write
74 ROS 0 Read
73 ROS 0 Special transaction
72 ROS 0 Clean Line Replace
71 ROS 0 Purge Translation Cache
70 ROS 0 Bus Invalidate Line
69 ROS 0 SNC deferred
68 ROS 0 SNC asserted GSEQ.
67 ROS 0 Received HITM Snoop Result.
66 ROS 0 SNC issued Hardfail Response.
65 ROS 0 SNC issued Deferred Response.
64 ROS 0 SNC issued No Data Response.
63 ROS 0 SNC issued Retry Response.
62:60 ROS 0 Data length.
59:52 ROS 0 Byte enables.
51 ROS 0 SNC will assert TRDY#.