Datasheet

Configuration Registers
3-40 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.9.6 NRECFSB: Non-recoverable Error Control Information of
Processor Bus
This register latches the control information for the first fatal processor bus error detected by the
SNC. For LPC synch errors, only the address, write, and read fields will be logged. This register is
not valid until 10 cycles after the response phase of the transaction logged. The contents of this
register is only valid when one of the errors that set this register is logged in the FERRST register.
50:41 ROS 0 Defer ID.
40:0
RWS/
ROS
0
A[43:3]:
This field is used for address logging and is not writable. For non-coherent
and I/O write transactions on the SP, this address is the same as the one in
the SP request packet. A[6:3]#, A[5:3]#, A[4:3]#, or A[3]# may be zeroed to
satisfy burst ordering requirements.
Device: NodeID
Function: 0
Offset: CCh(31:0), D0h(63:32), D4h(95:64) (Continued)
Bit Attr Default Description
Device: NodeID
Function: 0
Offset: DCh(31:0), E0h(63:32), E4h(95:64)
Bit Attr Default Description
95:77 RV 0 Reserved
76 ROS 0 SNC initiated this transaction
75 ROS 0 Write
74 ROS 0 Read
73 ROS 0 Special transaction
72 ROS 0 CLR
71 ROS 0 Purge TC
70 ROS 0 BIL
69 ROS 0 SNC deferred
68 ROS 0 SNC asserted GSEQ
67 ROS 0 Received HITM Snoop Result
66 ROS 0 SNC issued Hardfail Response
65 ROS 0 SNC issued Deferred Response.
64 ROS 0 SNC issued No Data Response.
63 ROS 0 SNC issued Retry Response.
62:60 ROS 0 Data length.
59:52 ROS 0 Byte enables.
51 ROS 0 SNC will assert TRDY#.