Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-41
Configuration Registers
3.9.7 RECSPP: Recoverable Error Control Information of SPP
This register latches control information for the first non-fatal error detected in the scalability port
protocol layer and configuration accesses. The contents of this register is only valid when one of
the errors that set this register is logged in the FERRST register.
3.9.8 NRECSPP: Non-recoverable Error Control Information of
SPP
This register latches control information for the first fatal error detected in the scalability port
protocol layer and configuration accesses. The contents of this register is only valid when one of
the errors that sets this register is logged in the FERRST register. Not all errors have logs (See
Table 6-1 “Intel® E8870 Chipset Errors” ).
3.9.9 RED: Non-Fatal Error Data Log
This register latches information for the first data error detected by the SNC that is not an SP
physical layer or memory read error. See Section 6.5, “Chipset Error Record” for a listing of the
errors that use this log.
The contents of this register is only valid when one of the errors that set this register is logged in
the FERRST register. The contents of this register is defined 10 clocks after the error is detected,
and is not changed until the bit is cleared from the FERRST register.
50:41 ROS 0 DID[9:0].
40:0
RWS/
ROS
0
A[43:3]:
This field is used for address logging and is not writable. For non-coherent
and I/O write transactions on the SP, this address is the same as the one in
the SP request packet. A[6:3]#, A[5:3]#, A[4:3]#, or A[3]# may be zeroed to
satisfy burst ordering requirements.
Device: NodeID
Function: 0
Offset: DCh(31:0), E0h(63:32), E4h(95:64) (Continued)
Bit Attr Default Description
Device: NodeID
Function: 2
Offset: 40h(31:0), 44h(63:32)
Bit Attr Default Description
63:0 ROS 0 SP request/response header or internal request/response header.
Device: NodeID
Function: 2
Offset: 48h(31:0), 4Ch(63:32)
Bit Attr Default Description
63:0 ROS 0 SP request/response header or internal request/response header.