Datasheet

Configuration Registers
3-42 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.9.10 REDSPL[1:0]: SP Non-fatal Error Data Log
This register latches Syndrome and ECC information for the first ECC error detected on incoming
SP data. See Section 6.5, “Chipset Error Record” for a listing of the errors that use this log.
The contents of this register is only valid when one of the errors that set this register is logged in
the FERRST register. The contents of this register is defined 10 clocks after the error is detected,
and is not changed until the bit is cleared from the FERRST register.
3.9.11 RECSPL[1:0]: Recoverable Error Control Information of
SP[1:0]
This register latches the control information for the first non-fatal error detected by the physical
layers of Scalability Ports 0 and 1. The contents of this register is only valid when one of the errors
that set this register is logged in the FERRST register.
Device: NodeID
Function: 2
Offset: 50h(31:0), 54h(63:32),58h(71:64)
Bit Attr Default Description
71:64 ROS 0 DEP[7:0]
63:0 ROS 0
D[63:0]
Data in error.
This could be the upper half or the lower half of the data bus.
Device: NodeID
Function: 2 (REDSLP0), 3(REDSPL1)
Offset: CCh
Bit Attr Default Description
15:8 ROS 0
Syndrome
This field is the calculated syndrome. This field points to the error type (multi
or single bit) and the data bit in error for single-bit errors.
7:0 ROS 0
ECC
This field is the ECC packet received on the SP for the flit in error.
Device: NodeID
Function: 2(SP0), 3(SP1)
Offset: C4h(31:0), C8h(63:32)
Bit Attr Default Description
63:0 ROS 0
SP request/response header or SP PHIT#, PHIT parity and PHIT, SP LLR
retry counts.