Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-43
Configuration Registers
3.9.12 RECMEM: Recoverable Error Control Information of
Memory
This register latches control information for the first non-fatal memory error detected by the SNC.
The address of the error can be inferred from the MIR and MIT register settings. The contents of
this register is only valid when one of the errors that set this register is logged in the FERRST
register.
3.9.13 REDMEM: Memory Read Data Error Log
This register latches data information for the first memory read error detected by the SNC. The
contents of this register must be valid when a memory read or scrub error is logged in the FERRST.
The contents of this register is defined 10 clocks after the error is detected, and is not changed until
the bit is cleared from the FERRST register.
The code used to protect memory is the Server ECC code described in Section 5.2.4, “Memory
Error Correction Code.”
Device: NodeID
Function: 1
Offset: E0h(31:0), E4h(63:32)
Bit Attr Default Description
63:40 RV 0 Reserved
39 ROS 0
Channel
This identifies one of the two DDR channels on each DMH on which the error
occurred.
38:34 ROS 0
Device
This identifies the DIMM selected by each DMH in which the error occurred
33:28 ROS 0 Bank
27:13 ROS 0
Row
See Table 5-4, “Bits Used in MCP Packet for Different DDR Technologies.”
12:0 ROS 0
Column
See “Fixed Field” in Section 5.3.2.5, “DDR Address Bit Mapping.” CA[10] is
always set to indicate auto-precharge.
Device: NodeID
Function: 1
Offset:D4h(31:0), D8h(63:32), DCh(95:66)
Bit Attr Default Description
95:66 RV 0 Reserved
65:64 ROS 0
Checkword
Identifies the checkword in error. Table 3-8 defines the encodings. The SNC
transfers critical 64-bytes first, so the half of the cacheline containing the
requested address will be in the first transfer.