Datasheet

Configuration Registers
3-44 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.10 Performance Monitoring Registers
3.10.1 PERFCON: Performance Monitor Master Control
The PERFCON register is a global register used to indicate event status of the performance counter
logic in the component and provides global control of the counters. Event count status bits are
cleared via the associated PMR register for the counter, or by starting a new sample. PERFCON
also provides the ability to control the EV pins from the SNC. The event pins are bidirectional open
drain signals, so that any component or external test device can drive the pin active (low state).
These pins may be connected to interrupts within the system. A usage model for the event pins is
for one event pin (EV0) to be used as the control to start and stop the sample interval, and another
event pin (EV1) to be used to report overflow or max count compare status, for all enabled counters
throughout the E8870 chipset-based system.
63:32 ROS 0
Syndrome
The bit in error can be calculated from this field and the Locator field.
Section 5.2.4, “Memory Error Correction Code” describes the H matrix used
for this calculation.
31:0 ROS 0
Locator
The Server ECC Locator which identifies the symbol in error for correctable
errors. Exactly one bit should be set if the error is correctable.
Bit Symbol
0 RAMBUS0, Symbol A
1 RAMBUS0, Symbol B
2 RAMBUS0, Symbol C
...
7 RAMBUS0, Symbol H
8 RAMBUS1, Symbol A
...
31 RAMBUS3, Symbol H
Table 3-8. Checkword Encoding
Checkword SNC
00 First checkword in first transfer.
01 Second checkword in first transfer.
10 First checkword in second transfer.
11 Second checkword in second transfer.
Device: NodeID
Function: 1
Offset:D4h(31:0), D8h(63:32), DCh(95:66) (Continued)
Bit Attr Default Description