Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-45
Configuration Registers
Device: NodeID
Function: 3
Offset: 50h
Bit Attr Default Description
15:10 RV 0 Reserved
9RO0
SPPM Count Status
The OR of both Event Status bits reported by either SPPM module for an
overflow or max comparison condition, i.e.,
SPPMR[0].EventStatus[0] OR
SPPMR[0].EventStatus[1] OR
SPPMR[1].EventStatus[0] OR
SPPMR[1].EventStatus[1]
The status condition can be cleared by writing zeros to the Event Status field of
the affected PMR register.
8RO0
FSBPM Count Status
The OR of both Event Status bits reported by either FSBPM module for an
overflow or max comparison condition, i.e.,
FSBPMR[0].EventStatus[0] OR
FSBPMR[0].EventStatus[1] OR
FSBPMR[1].EventStatus[0] OR
FSBPMR[1].EventStatus[1]
The status condition can be cleared by writing zeros to the Event Status field of
the affected PMR register.
7RO0
Hot Page Status
Status reported by Hot Page (see HPPMR) module for a timer completion or
max comparison condition.
HPPMR[0].Max Count Compare Status OR
HPPMR[0].Timer Completion Status OR
HPPMR[1].Max Count Compare Status OR
HPPMR[1].Timer Completion Status
The status condition can be cleared by writing zeros to the Max Count Compare
Status field and the TimerCompletion Status field of the HPPMR register.
6RO0
Timer Completion Status
This is a duplication of the Timer Completion Status bit of the PTCTL register.
It is cleared by writing a’0’ to the Timer Completion Status bit in the PTCTL
register.
5:2 RW 0
EV[3:0]# Control
A’1’ will activate the associated event signal, and ’0’ will inactivate the signal.
When using the Interval Timer this field must be set to the inactive state “0000”.
xxx1 Drives EV[0]# event signal active
xx1x Drives EV[1]# event signal active
x1xx Drives EV[2]# event signal active
1xxx Drives EV[3]# event signal active.