Datasheet
Configuration Registers
3-46 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.10.2 PTCTL: Timer Control
The countdown timer can be used to control the sample interval for the SNC, as well as throughout
the chipset. The timer can be programmed to assert an EV pin when active (see Timer Control
Output field), and counters in the chipset can be programmed to be enabled on the same EV pin.
This type of control allows fine-grained sampling (at levels that cannot be accomplished by a
software-only control).
The timer can also be placed in a repetitive mode where the sample interval is repeated (until the
timer is disabled). This feature is used in conjunction with the max-compare (CMP) capabilities in
the event modules provides the capability of gathering data on event frequencies over discrete time
intervals
.
The timer can be set to increment for each clock, or a multiple of clock periods (see Timer
Prescale field). The maximum increment is 128 cycles, providing a total timer period of
approximately 40 minutes.
1RW0
Local Count Enable
Setting this bit to a ’1’ will enable any counter on this component which has
“local count enable” assigned as the enable source in the CE_Src field of its
individual PMR register. Writing a ’0’ to this bit will disable the counters.
Note: When using the Interval Timer this field must be set to ’0’.
0RW0
Reset
Setting this bit to a ’1’ will reset all perfmon registers in this component to the
default state. This includes timer registers, hotpage registers, and PM module
registers. This bit is automatically cleared to ’0’ by hardware after the registers
are reset.
Note: This register is not affected.
Device: NodeID
Function: 3
Offset: 50h (Continued)
Bit Attr Default Description
Device: NodeID
Function: 3
Offset: 52h
Bit Attr Default Description
15 RW 0
Timer Status Output Enable
1 = Enable Timer Status Output as defined in bits 5:4 of this register.
14 RV 0 Reserved
13:11 RW 0
Timer Disable Source
This field selects a source to disable the interval timer. The “Timer Enable”
control (bit 0) and “Repetitive Mode” control (bit 7) will be disabled if the
selected signal is activated. The activation of the selected signal will disable
the interval timer, i.e. the control is edge sensitive.
000 No disable source
001 Any local counter status condition on this component
010 GE0 (Global DFT/Debug Event 0)
011 GE1 (Global DFT/Debug Event 1)
100 EV[0]#
101 EV[1]#
110 EV[2]#
111 EV[3]#