Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-47
Configuration Registers
10:8 RW 0
Timer Prescale
This field determines the rate at which the timer will count in terms of the SNC
internal clock.
000 1x
001 2x
010 4x
011 8x
100 16x
101 32x
110 64x
111 128x
7RW0
Repetitive Mode
Setting this bit to ’1’ enables the interval timer repetitive mode. In the repetitive
mode, when the interval timer completes a time interval, it automatically
restarts another time interval after a delay of 12 clocks. This is repeated
continuously until this bit is cleared to a ’0’ or a signal selected by the Timer
Disable Source field becomes active, which will clear this bit to a ’0’. The
interval timer is loaded with the contents of the PMINIT register at the start of
each time interval. Timer Completion Status is not reported nor is the Timer
Enable bit cleared in repetitive mode when the interval timer completes a time
interval.
6RW0
Timer Completion Status
0 - Timer sample period not complete or is inactive
1 - Timer sample period complete
This bit is sticky in that once the timer completion occurs, it remains active until
it is cleared by writing a’0’ to this bit, or when another time interval is started by
setting the Timer Enable bit in this register. This timer status is also visible in
the PERFCON register.
5:4 RW 0
Timer Status Output
When not in repetitive mode, timer completion status is reported in PERFCON.
In addition, timer completion status can be driven on an event pin. The “Timer
Status Output Enable” control in bit 15 of this register must be set, otherwise
no event pins will be driven.
00 - timer completion status driven on EV[0]#
01 - timer completion status driven on EV[1]#
10 - timer completion status driven on EV[2]#
11 - timer completion status driven on EV[3]#
3:1 RW 0
Timer Control Output
This field selects how the Interval Timer controls the enables to the counters.
When the timer is > 0 and the timer is enabled, this field allows the timer to
control the EV pins or the “local count enable.” The PERFCON register is not
used for control when using the timer.
000 “Local Count Enable” active when “Timer Enable” and Timer value > 0
001 Reserved
010 Reserved
011 Reserved
100 EV[0]# active when “Timer Enable” and Timer value > 0
101 EV[1]# active when “Timer Enable” and Timer value > 0
110 EV[2]# active when “Timer Enable” and Timer value > 0
111 EV[3]# active when “Timer Enable” and Timer value > 0
0RW0
Timer Enable
This bit is set to enable the counter. This is cleared by hardware when the
contents of the timer underflows and repetitive mode is disabled. In repetitive
mode, software must clear this bit to disable counting.
Device: NodeID
Function: 3
Offset: 52h (Continued)
Bit Attr Default Description