Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-49
Configuration Registers
Note: For these first two methods, bit 31 of the PMC should typically be set to 0. The comparison does
include bit 31 (overflow) of the PMD counter, but since the overflow sets the counter status, a
subsequent comparison will not affect the status condition.
The third mode is an address comparison mode. PMD0 compares on addresses greater than the
PMC0 register and PMD1 compares on addresses less than or equal to PMC1. The “AND” of these
two comparisons is the address range comparison and qualifies the other match event conditions
for both counters. Note that the contents of PMC is compared to A[38:7]#.
3.10.7 FSBPMR[1:0]: Processor Bus Performance Monitor
Response
The PMR register controls operation of its associated counter, and provides overflow or max
compare status information.
Device: NodeID
Function: 3
Offset: A4h (FSBPMC0), E4h(FSBPMC1)
Bit Attr Default Description
31:0 RW FFFF_FFFFh Counter Compare Value.
Device: NodeID
Function: 3
Offset: A0h (FSBPMR0), E0h(FSBPMR1)
Bit Attr Default Description
31:26 RV 0 Reserved
25:24 RW 0
Event Group Selection
Selects which PME register to use for event decodes
00 - Bus events (FSBPMEH and FSBPMEL registers)
01 - Resource events (FSBPMER register)
10 - Resource utilizations (FSBPMEU register)
11 - Reserved