Datasheet

viii Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Figures
1-1 Typical Itanium
®
2-Based Server Configuration.................................................1-2
1-2 Scalable Node Controller Queueing Structures .................................................1-3
1-3 Scalable Node Controller Interfaces ..................................................................1-4
4-1 System Memory Address Space........................................................................4-1
4-2 Firmware Map Example using Intel
®
E8870 Chipset and Intel 82802 FWH
with Local Firmware Enabled.............................................................................4-5
4-3 Firmware Map Example using Intel
®
E8870 Chipset and Intel 82802 FWH
with Local Firmware Disabled ............................................................................4-6
4-4 Use of MIRs to Interleave Blocks of Varying Size Across Different Nodes......4-10
4-5 Reflections Used to Recover Memory Behind Enabled Spaces ......................4-11
4-6 System I/O Address Space..............................................................................4-19
5-1 Error Correction Code Layout on Main Channels 0 and 1 .................................5-6
5-2 Error Correction Code Layout on Main Channels 2 and 3 .................................5-7
5-3 Typical DDR-SDRAM Memory System............................................................5-10
7-1 Clock Distribution Scheme.................................................................................7-2
7-2 Differential Bus Clock to Processors and SNC ..................................................7-3
7-3 Firmware Hub Clocks.........................................................................................7-4
8-1 Power-up Reset Timing......................................................................................8-3
8-2 Hard Reset Deassertion Timing.........................................................................8-3
8-3 Warm RESETI# Sampling..................................................................................8-6
8-4 Synchronization Point for Determinism..............................................................8-7
8-5 Reset Re-triggering Limitations..........................................................................8-9
8-6 Deterministic Hard Reset Timing .....................................................................8-10
8-7 Simplest Power Good Distribution ...................................................................8-13
8-8 Basic System Reset Distribution......................................................................8-14
8-9 Basic System Reset Timing .............................................................................8-14
9-1 TAP DC Thresholds ...........................................................................................9-9
9-2 TAP and SMBus Valid Delay Timing Waveform ..............................................9-10
9-3 TCK and SM_CLK Clock Waveform ................................................................9-11
9-4 Generic Differential Clock Waveform...............................................................9-16
10-1 1357-ball OLGA2b Package Dimensions – Top View......................................10-1
10-2 1357-ball OLGA2b Package Dimensions – Bottom View ................................10-2
10-3 1357-ball OLGA2b Solder Balls Detail.............................................................10-3
11-1 TAP Controller Signals.....................................................................................11-1
11-2 Simplified Block Diagram of TAP Controller.....................................................11-2
11-3 TAP Controller State Diagram..........................................................................11-3
11-4 TAP Instruction Register ..................................................................................11-6