Datasheet

Configuration Registers
3-50 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
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Compare Mode
This field defines how the PMC (compare) register is to be used.
00 - Compare mode disabled (PMC register not used)
01 - Max compare only: The PMC register value is compared with the counter
value. If the counter value is greater, the Count Compare Status (bit 13) of the
“Event Status” field of this register will be set.
Note: Bit 31 of the PMC should typically be set to ’0’. The comparison does
include bit 31 (overflow) of the PMD counter, but since the overflow sets the
counter status, a subsequent comparison will not affect the status condition.
10 - Max compare with update of PMC at end of sample: The PMC register
value is compared with the counter value, and if the counter value is greater,
the PMC register is updated with the counter value.
Note: The Event Status field is not
affected in this mode. Bit 31 of the PMC
should typically be set to ’0’. The comparison does include bit 31 (overflow) of
the PMD counter, but since the overflow sets the counter status, a subsequent
comparison will not affect the status condition.
11 - Address compare mode where the PMC register is compared with the
address field. Counter 0 of a counter pair will compare on an address greater
than the register, and counter 1 will compare on an address equal to or lesser
than the register (inverse of greater than). When both comparisons are valid,
an address range comparison qualification is generated. This mode will cause
the results of the address range comparison to be AND’ed with the event
qualification specified in the selected PME register of each counter. The Event
Status field is not
affected in this mode.
Note: Address comparison range is A[38:7]#.
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Reset Event Select
Counter and event status will reset and counting will continue.
Note: Delay from an event causing an EV pin activation until reset of the
counter is 13 clocks.
000 - No reset condition
001 - Partner event status: When the partner counter causes an event status
condition to be activated, either by a counter overflow or max comparison,
then this counter will reset and continue counting.
010 - Partner PME register event: When the partner counter detects a match
condition which meets its selected PME register qualifications, then this
counter will reset and continue counting.
011 Reserved
100 EV[0]#
101 EV[1]#
110 EV[2]#
111 EV[3]#
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Count Event Select
Selects the condition for incrementing the performance monitor counter.
000 PME register event
001 Partner event status (max compare or overflow)
010 All clocks when enabled
011 Reserved
100 EV[0]#
101 EV[1]#
110 EV[2]#
111 EV[3]#
Device: NodeID
Function: 3
Offset: A0h (FSBPMR0), E0h(FSBPMR1) (Continued)
Bit Attr Default Description