Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-51
Configuration Registers
15:14 RW 0
Count Mode
00 - Count event selected by Count Event Select field.
01 - Count clocks after event selected by Count Event Select field.
10 - Count transaction length, in quad words, of event defined by the Bus
Events PME registers (FSBPMEL and FSBPMEH.)
Note: The Count Event field and Event Group Selection fields should select
the Bus Events PME registers.
11 - Reserved
13:12 RW 0
Event Status
This status bit captures an overflow or count compare event. The Event Status
Output field can be programmed to allow this bit to be driven to an external
event pin.
00 - No event
x1 - Overflow – The PMD counter overflow status. (Write’0’ or start an interval
to clear.)
1x - Count compare – PMD counter greater than PMC register when in
compare mode. (Write’0’ or start an interval to clear.)
This bit is sticky in that once an event is reported the status remains even
though the original condition is no longer valid. This bit can be cleared by
software or by starting a sample. Event status is always visible in the
PERFCON register, except if “Event Status Output” field is in cascade mode.
Note: If in address compare mode (compare mode = 11), the count compare
bit is not activated.
11:9 RW 0
Event Status Output
This field selects where the event status is reported.
000 Event status reported only in PERFCON register (address comparison
not reported)
001 Cascade mode, status not reported
100 Event status or address comparison in PERFCON and on EV[0]# pin
101 Event status or address comparison in PERFCON and on EV[1]# pin
110 Event status or address comparison in PERFCON and on EV[2]# pin
111 Event status or address comparison in PERFCON and on EV[3]# pin
8:5 RW 0
CD_Src: Counter Disable Source
These bits control which input disables the counter.
Note: If the “Enable Source” is inactive counting is also disabled. (Delay from
an event causing an EV pin activation until disable of the counter is
13 clocks.)
1xxx EV[3]# pin
x1xx EV[2]# pin
xx1x EV[1]# pin
xxx1 EV[0]# pin
4:2 RW 0
CE_Src: Counter Enable Source
These bits identify which input enables the counter. Default value disables
counting.
000 Disabled
001 PERFCON local_count_enable field
010 Partner event status (max compare, overflow, cascade)
011 Reserved
100 EV[0]# pin
101 EV[1]# pin
110 EV[2]# pin
111 EV[3]# pin
Device: NodeID
Function: 3
Offset: A0h (FSBPMR0), E0h(FSBPMR1) (Continued)
Bit Attr Default Description