Datasheet

Configuration Registers
3-52 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.10.8 FSBPMEL[1:0]: Processor Bus Performance Monitor
Events LO
This register is the least significant of the two used to select bus events. Use of the event registers is
mutually exclusive with other processor bus event registers. Each major bit field in this register is
AND’ed with other major bit fields (in both the FSBPMEL and FSBPMEH registers) to select the
event. If one field does not match, then the counter will not count.
1RW0
Clear Overflow
This bit clears overflow bit in associated PMD counter. The counters
continues counting. This bit is cleared by hardware when the operation is
complete.
0RW0
Reset
Setting this bit resets all registers associated with this counter to the default
state. It does not change this PMR register since any desired value can be
loaded while setting the Reset bit. This Reset bit will by cleared after the reset
is completed. For diagnostic purposes, the contents of the other registers can
be read to verify operation of this bit.
Note: There is also a reset bit in the PERFCON register which clears all
counter registers including the PMR.
Device: NodeID
Function: 3
Offset: A0h (FSBPMR0), E0h(FSBPMR1) (Continued)
Bit Attr Default Description
Device: NodeID
Function: 3
Offset: ACh (FSBPMEL0), ECh(FSBPMEL1)
Bit Attr Default Description
31:30 RW 0
LOCK
01 - select unlocked cycles
10 - select locked cycle
29:23 RW 0
Snoop Phase Signals (AND’ed Group)
1xxxxxx normal inorder (no snoop signals during snoop phase)
x1xxxxx HITM
xx1xxxx HIT
xxx1xxx DHIT (Deferred Phase Data Hit – cache cannot go owned.
OR'ed with other group qualifications, not AND’ed)
xxxx1xx DEFER (Signal)
xxxxx1x VSBL (Write visibility guaranteed)
xxxxxx1 TND (Purge TC Not Done)
22:18 RW 0
Completion Status (AND’ed Group)
1xxxx Retried – all
x1xxx Retried – address collision
xx1xx In Order (Non-deferred)
xxx1x Deferred
xxxx1 Hard Failure