Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-57
Configuration Registers
3.10.12 SPPMD[1:0]: SP Performance Monitor Data
This is the performance monitor counter. The overflow bit can be cleared via the PMR register
without perturbing the value of the counter. This counter is reset at the beginning of a sample
period unless preloaded since a prior sample. Therefore, the counter can be preloaded to cause an
early overflow, otherwise it will be reset at the start of a sample period.
3.10.13 SPPMC[1:0]: SP Performance Compare
The compare register can be used three ways as selected in the “Compare Mode” field of the PMR
register. First, when PMD is incremented, the value of PMD is compared to the value of PMC. If
PMD is greater than PMC, this status is reflected in the PERFCON register and/or on EV pins as
selected in the “Event Status Output” field of the PMR register. Secondly, update the PMC register
with the value of PMD if the PMD register exceeds the contents of PMC.
Note: For these first two methods, bit 31 of the PMC should typically be set to 0. The comparison does
include bit 31 (overflow) of the PMD counter, but since the overflow sets the counter status, a
subsequent comparison will not affect the status condition.
The third mode is an address comparison mode. PMD0 compares on addresses greater than the
PMC0 register and PMD1 compares on addresses less than or equal to PMC1. The “AND” of these
two comparisons is the address range comparison and qualifies the other match event conditions
for both counters. Note that the contents of PMC is compared to A[38:7]#.
Device: NodeID
Function: 2
Offset: E8h (SPPMD0), F8h (SPPMD1)
Bit Attr Default Description
31 RW 0 Overflow.
30:0 RW 0 Current Counter Value.
Device: NodeID
Function: 2
Offset: E4h (SPPMC0), F4h (SPPMC1)
Bit Attr Default Description
31:0 RW FFFF_FFFFh Counter Compare Value.