Datasheet

Configuration Registers
3-58 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.10.14 SPPMR[1:0]: SP Performance Monitor Response
The PMR register controls operation of its associated counter, and provides overflow or max
compare status information.
Device: NodeID
Function: 2
Offset: E0h (SPPMR0), F0h(SPPPMR1)
Bit Attr Default Description
31:26 RV 0 Reserved
25 RW 0
Req/RspType Bus Select
0 = Request Bus
1 = Response Bus
24 RW 0 This bit has no effect on SNC operation.
23:22 RW 0
Compare Mode
This field defines how the PMC (compare) register is to be used.
00 - compare mode disabled (PMC register not used)
01 - Max compare only: The PMC register value is compared with the counter
value. If the counter value is greater then Count Compare Status (bit 13) of
the “Event Status” field of this register will be set.
Note: Bit 31 of the PMC should typically be set to’0’. The comparison does
include bit 31 (overflow) of the PMD counter, but since the overflow sets the
counter status, a subsequent comparison will not affect the status condition.
10 - Max compare with update of PMC at end of sample: The PMC register
value is compared with the counter value, and if the counter value is greater,
the PMC register is updated with the counter value. The Event Status field is
not
affected in this mode.
11 - Address compare mode where the PMC register is compared with the
address field. Counter 0 of a counter pair will compare on an address greater
than the register, and counter 1 will compare on an address equal to or lesser
than the register (inverse of greater than). When both comparisons are valid,
an address range comparison qualification is generated. This mode will
cause the results of the address range comparison to be AND’ed with the
event qualification specified in the selected PME register of each counter.
The Event Status field is not
affected in this mode. The address comparison
range is A[38:7]#.
21:19 RW 0
Reset Event Select
Counter and event status will reset and counting will continue.
000 No reset condition
001 Partner’s event status: When the partner counter causes an event
status condition to be activated, either by a counter overflow or max
comparison, then this counter will reset and continue counting.
010 Partners PME register event: When the partner counter detects a
match condition which meets its selected PME register qualifications,
then this counter will reset and continue counting.
011 Reserved
100 EV0 pin
101 EV1 pin
110 EV2 pin
111 EV3 pin