Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheetix
Tables
1-1 Chipset Component Markings............................................................................1-1
2-1 Buffer Technology Types ...................................................................................2-1
2-2 Buffer Signal Directions......................................................................................2-2
2-3 Signal Naming Conventions...............................................................................2-2
2-4 SNC Signal List..................................................................................................2-2
3-1 Register Attributes Definitions............................................................................3-1
3-2 Register Grouping by Function...........................................................................3-4
3-3 MAR Register Mappings ....................................................................................3-8
3-4 MIT Definition for DDR SDRAM .......................................................................3-14
3-5 Legal Combinations of TRW, TWR ..................................................................3-18
3-6 DDR IOP Decodes ...........................................................................................3-21
3-7 Enabling the LPC/FWH Interface .....................................................................3-31
3-8 Checkword Encoding .......................................................................................3-44
4-1 MAR Settings .....................................................................................................4-2
4-2 SNC Memory Mapping Registers.....................................................................4-12
4-3 SPS Memory Mapping Registers .....................................................................4-13
4-4 SIOH Memory Mapping Registers....................................................................4-13
4-5 Destinations (ATTR).........................................................................................4-13
4-6 Address Disposition for Processor ...................................................................4-14
4-7 Intel
®
E8870 Chipset SAPIC Interrupt Message Routing and Delivery............4-16
4-8 Address Disposition for Inbound Transactions.................................................4-16
5-1 General Memory Characteristics........................................................................5-1
5-2 Indices to Re-Ordering Queues..........................................................................5-3
5-3 DDR-SDRAM Total Memory Per SNC .............................................................5-10
5-4 Bits Used in MCP Packet for Different DDR Technologies ..............................5-12
5-5 DDR Address Bit Mapping ...............................................................................5-12
5-6 Interleave Field Mapping for DDR....................................................................5-13
5-7 MCP Bits Forced by RAFIX and DIV Fields for DIMM Splitting........................5-14
6-1 Intel
®
E8870 Chipset Errors ...............................................................................6-2
6-2 RAS Roles of Different System Components...................................................6-11
6-3 Intel
®
E8870 Chipset Error Status and Log Registers......................................6-14
6-4 E8870 Chipset Errors, Transaction, and Class Information .............................6-17
6-5 Control: SP Request Header Error Log............................................................6-20
6-6 Control: SP Response Header Error Log.........................................................6-20
6-7 Link Layer Errors: Data Log Fields...................................................................6-21
6-8 Link Layer Errors: LLR and Phit Fields.............................................................6-21
8-1 Intel
®
E8870 chipset Reset Types......................................................................8-1
8-2 Reset Response Sequences Summary .............................................................8-2
8-3 Power-up and Hard Reset Deassertion Timings................................................8-4
8-4 Critical Initialization Timings...............................................................................8-4
9-1 Absolute Maximum Non-operational DC Ratings at the Package Pin................9-1
9-2 Voltage and Current Specifications....................................................................9-1
9-3 SNC System Bus Signal Groups........................................................................9-3
9-4 SNC AGTL+ DC Parameters .............................................................................9-4
9-5 Scalability Port Interface Signal Group...............................................................9-4
9-6 DMH Main Channel Signal Groups ....................................................................9-5
9-7 Main Channel Vref Specification ........................................................................9-5
9-8 RSL Data Group, DC Parameters......................................................................9-6
9-9 RSL Clocks, DC Parameters..............................................................................9-6