Datasheet
Configuration Registers
3-62 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
17:15 RW 0
Resolution
Determines the address range for each counter
000 64-bytes
001 4 KB
010 128 KB
011 8 MB
100 256 MB
14 RW 0
Filter Select (Conditioned Addresses)
0 = All transaction types. The retried transactions are also counted. To filter
retried transactions, set this bit and use the FSBPME0 “completion
status” field to eliminate retried cycles.
1 = Transactions qualified with the event selection of Processor Bus
Performance Module 0.
13 RW 0
Max Count Compare Status
This bit is sticky in that once an event is reported the status remains even
though the original condition is no longer valid. This bit can be cleared by
software (write a ’0’) or by starting a sample. Hot Page Max Count status is
always visible in the PERFCON register.
12 RO 0
Timer Completion Status
This bit is a reflection of the Timer Underflow Status bit in the PTCTL register
(bit 6). It can be cleared by writing a ’0’ to bit 6 of the PTCTL register.
11:9 RW 0
Event Status Output
This field selects how the Timer Completion Status is reported.
000 Hot Page status reported only in PERFCON register
100 Hot Page status on EV[0]# pin
101 Hot Page status on EV[1]# pin
110 Hot Page status on EV[2]# pin
111 Hot Page status on EV[3]# pin
8:5 RW 0
CD_Src: Counter Disable Source
These bits control which input disables the counter.
Note: If the “Enable Source” is inactive counting is also disabled.
1xxx EV3 pin
x1xx EV2 pin
xx1x EV1 pin
xxx1 EV0 pin
4:2 RW 0
CE_Src: Counter Enable Source
These bits identify which input enables the counter. Default value disables
counting.
000 Disabled
001 PERFCON or PTCTL Local Count Enable field
010 Reserved
011 Enable. (writing a one causes the Hot Page counters to be enabled
immediately.)
100 EV0# pin
101 EV1# pin
110 EV2# pin
111 EV3# pin
1RW0
AutoZero
Writing a ’1 will clear all SRAM entries. This bit is reset to zero after the
operation is complete.
0RW0
Reset
Set hotpage registers to default values: 1 = reset. Does not reset this register
nor the counter array. This bit is cleared by hardware.
Device: NodeID
Function: 3
Offset: 60h (Continued)
Bit Attr Default Description