Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 4-1
System Address Map 4
4.1 Memory Map
The Itanium 2 processor provides address bits for a 50-bit address space. The SNC support 44 bits
of addressing
1
.
The E8870 chipset treats accesses to several address ranges in different ways. There are fixed
ranges like the compatibility region below 1 MB, interrupt delivery range, and the system region
located in the 32 MB directly below 4 GB. In addition, there is a variable region for memory-
mapped I/O. The locations of these ranges in the memory map are illustrated in Figure 4-1.
In this chapter, we are going to use the Intel E8870SP scalability port switch (SPS) as an example
to illustrate one possible implementation. Other SP switches will have different implementations.
1. The SNC does not connect to A[49:44]. An illegal address (A[49:44] > 0) may not be detected by the SNC.
Figure 4-1. System Memory Address Space
001144
High
Extended
Memory
Medium
Extended
Memory
Compatibility
Area
4 GB-16 MB
16 TB-4 GB
15 MB
1 MB
FFF_FFFF_FFFFh
1_0000_0000h
FFFF_FFFFh
10_0000h
F_FFFFh
E_0000h
C_0000h
A_0000h
0
System
Memory
System
Memory
FFF_0000_0000h
FF_FFFF_FFFFh
M x 4 GB
1_0000_0000h
FFFF_FFFFh
FFC0_0000h
FF00_0000h
FEC0_0000h
FE00_0000h
High MMIO
MMCFG
Local Firmware
Global Firmware
Processor
Chipset
Low MMIO
64 MB
4 MB
12 MB
4 MB
12 MB
N x 16 MB
400_0000h
System
BIOS
C and D
Segments
VGA
Memory
DOS
Region
128K
128K
128K
640K
Areas are not
drawn to scale.
Low
Extended
Memory