Datasheet

System Address Map
4-2 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
4.1.1 Compatibility Region
This is the range from 0 to 1 MB (0_0000h to F_FFFFh). Requests to the compatibility region are
directed to main memory, the compatibility bus, or the VGA device. Physical DRAM addressed by
requests in this region that are mapped to the compatibility bus is not recovered.
This region is divided into four ranges. Regions below 1MB that are mapped to memory are
accessible by the processors and by any PCI bus.
Note: DRAM that has a physical address between 0 and 1 MB must not be recovered, relocated or
reflected. This range must always be available to the OS as DRAM, even if addresses in this range
are sent to the compatibility bus or VGA or other non-DRAM areas at times.
4.1.1.1 DOS Region
DOS applications execute in the lowest 640 KB, in the address range 0h to 9_FFFFh. This range is
always mapped to main memory. Note that older chipsets allowed the range from 8_0000h to
9_FFFFh to be mapped to the compatibility bus. The E8870 chipset does not support this legacy
feature.
4.1.1.2 VGA Memory Range
The 128 KB Video Graphics Adapter Memory range (A_0000h to B_FFFFh) can be mapped to the
VGA device that may be on any Hub Interface, or it can be mapped to main memory. This space is
mapped to main memory at power-on.
BIOS must explicitly enable the VGA range before it can be used. This region can be redirected by
BIOS to point to any bus that has a VGA card. Only one bus per domain may be enabled for VGA.
4.1.1.3 MDA Memory Range
This is the range from B_0000h to B_7FFFh and is used for the monochrome region. If the MDA is
enabled, all requests in this range are sent to the SP with Attr = CB. If MDA is not enabled, this is
part of VGA space. The monochrome display adapter is always on the compatibility bus.
4.1.1.4 C and D Segments
Writes and reads may be directed to different destinations in the range C_0000h to D_FFFFh.
Typically, these blocks were used to shadow ISA device’s BIOS code. For the E8870 chipset, these
regions are used to provide address space to PCI devices requiring memory space below 1MB. The
range is divided into eleven subranges. There is one MAR field for each subrange that defines the
routing of reads and writes.
Table 4-1. MAR Settings
MAR value Writes Go To Reads Go To Result
00 Compatibility Bus Compatibility Bus Mapped to the Compatibility PCI
01 Compatibility Bus Main Memory Memory Write Protect
10 Main Memory Compatibility Bus In-line Shadowed
11 Main Memory Main Memory Mapped to main memory