Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 4-3
System Address Map
The default for these segments at power-on is that they are mapped read/write to the compatibility
bus. Software should not set cacheable memory attributes for any of these ranges unless both reads
and writes are mapped to main memory. In the write protect case, the E8870 chipset cannot
guarantee write protection if an Implicit write-back occurs. This will result in a write-back to
memory. If a Bus Read Invalidate Line or explicit write-back is issued, the E8870 chipset will
malfunction.
In the In-Line-Shadowed case, the E8870 chipset will complete operations, but does not guarantee
coherency. The E8870 chipset will complete, but does not guarantee the atomicity of locked access
to this range when writes and reads are mapped to separate destinations.
For Itanium 2-based systems, SNC MAR registers must be configured to map this range to main
memory.
4.1.1.5 System BIOS (E and F Segments)
The 128 KB region from E0000h to F_FFFFh is treated as a single block. Read/write attributes
defined in the MAR registers may be used to direct accesses to the compatibility bus or main
memory. At power-on, this area is mapped read/write to the firmware hub devices on the SNC.
When this region is mapped to the local FWH, this region is only accessible from the processors on
that node and not from processors on a different node, PCI or any other I/O device. When this
region is mapped to the ICH4 FWH, it may be accessed from any processor bus, but inbound
accesses will access main memory. This main memory would not be used in this case. When
accesses are directed to the SNC FWH port, this region addresses the same range as FFFE_0000h-
FFFF_FFFFh. This means A[31:20]# will be active on the LPC interface.
The default for these segments at power-on is that they are mapped read/write to the compatibility
bus. Software should not set cacheable memory attributes for any of these ranges unless both reads
and writes are mapped to main memory. In the write protect case, the E8870 chipset cannot
guarantee write protection if an implicit write-back occurs. This will result in a written back to
memory. If a Bus Read Invalidate Line or explicit write-back is issued, the E8870 chipset will
malfunction.
In the In-Line-Shadowed case, the E8870 chipset will complete operations, but does not guarantee
coherency. The E8870 chipset will complete, but does not guarantee the atomicity of locked access
to this range when writes and reads are mapped to separate destinations.
For Itanium 2-based systems, SNC MAR registers must be configured to map this range to main
memory.
4.1.2 System Region
The System Region occupies the 32 MB directly below the 4-GB address. It consists of sub-regions
for firmware, processor memory mapped functions, and E8870 chipset specific registers. All
memory in this system region must not be marked as write-back.
4.1.2.1 Local Firmware Range
The E8870 chipset supports 4 MB of firmware on the SNC FWH port. Processor requests in the
address range FFC0_0000h to FFFF_FFFFh are sent to the SNC FWH port if it is enabled.
Otherwise, the request is sent to the compatibility bus. Inbound accesses will be master aborted.
Only 4 MB is addressable on this interface, and only A[21:0]# are mapped to this interface.
A[31:23]# are set high except for A[22]#, which is controlled by the Feature Space Enable bit in
the SNC FSBC register.