Datasheet

[AK4646]
MS0557-E-06 2011/06
- 20 -
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in
Table 4, when the AK4646 is supplied stable clocks after PLL is
powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency is changed.
1) Setting of PLL Mode
R and C of
VCOC pin
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL
Reference
Clock Input
Pin
Input
Frequency
R[Ω]
C[F]
PLL Lock
Time
(max)
0 0 0 0 0 LRCK pin 1fs 6.8k 220n 160ms (default)
1 0 0 0 1 N/A - - - -
2 0 0 1 0 BICK pin 32fs 10k 4.7n 2ms
10k 10n 4ms
3 0 0 1 1 BICK pin 64fs 10k 4.7n 2ms
10k 10n 4ms
6 0 1 1 0 MCKI pin 12MHz 10k 10n 40ms
7 0 1 1 1 MCKI pin 24MHz 10k 10n 40ms
12 1 1 0 0 MCKI pin 13.5MHz 10k 10n 40ms
13 1 1 0 1 MCKI pin 27MHz 10k 10n 40ms
Others Others
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in
Table 5.
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency
0 0 0 0 0 8kHz (default)
1 0 0 0 1 12kHz
2 0 0 1 0 16kHz
3 0 0 1 1 24kHz
4 0 1 0 0 7.35kHz
5 0 1 0 1 11.025kHz
6 0 1 1 0 14.7kHz
7 0 1 1 1 22.05kHz
10 1 0 1 0 32kHz
11 1 0 1 1 48kHz
14 1 1 1 0 29.4kHz
15 1 1 1 1 44.1kHz
Others Others N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin)
When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and
FS2 bits. (
Table 6).
Mode
FS3 bit FS2 bit
FS1 bit FS0 bit
Sampling Frequency
Range
0
0 0
Don’t care
Don’t care
7.35kHz ≤ fs ≤ 12kHz
(default)
1
0 1
Don’t care
Don’t care
12kHz < fs ≤ 24kHz
2
1 0
Don’t care
Don’t care
24kHz < fs ≤ 48kHz
Others Others N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference: Clock: LRCK or BICK pin)