Specifications

ManualsBrandsMasterclock ManualsClockTCDS Series

4 ADC with PLL,

192 kHz, 24-Bit ADC

Data Sheet

AD1974

Rev. D Document Feedback

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FEATURES

Phase-locked loop generated or direct master clock

Low EMI design

107 dB dynamic range and SNR

−94 dB THD + N

Single 3.3 V supply

Tolerance for 5 V logic inputs

Supports 24 bits and 8 kHz to 192 kHz sample rates

Differential ADC input

SPI®-controllable for flexibility

Software-controllable clickless mute

Software power-down

Right justified, left justified, I

S, and TDM modes

Master and slave modes up to 16-channel input/output

Available in a 48-lead LQFP

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home Theater Systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD1974 is a high performance, single-chip ADC that pro-

vides four analog-to-digital converters (ADCs) with differential

inputs using the Analog Devices, Inc. patented multibit sigma-

delta (Σ-Δ) architecture. An SPI port is included, allowing a

microcontroller to enable mutes and adjust many other

parameters. The AD1974 operates from 3.3 V digital and analog

supplies. The AD1974 is available in a single-ended output

48-lead L Q F P.

The AD1974 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board phase-locked loop (PLL) to derive the

master clock from the LR clock or from an external crystal,

the AD1974 eliminates the need for a separate high frequency

master clock and can also be used with a suppressed bit clock.

The ADCs are designed using the latest continuous time archi-

tectures from Analog Devices to further minimize EMI. By

using 3.3 V supplies, power consumption is minimized, further

reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

QUAD

DEC

FILTER

48kHz/

96kHz/192kHz

SERIAL DATA PORT

DIGITAL AUDIO

INPUT/OUTPUT

PRECISION

VOLTAGE

REFERENCE

12.48MHz

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

CONTROL PORT

SPI

CONTROL DATA

INPUT/OUTPUT

AD1974

ADC

ANALOG

AUDIO

INPUTS

SDATA

OUT

CLOCKS

06614-001

Figure 1.

Summary of content (24 pages)

PAGE 1
4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 Data Sheet FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.
PAGE 2
AD1974 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 11 Applications ....................................................................................... 1 Analog-to-Digital Converters (ADCs) .................................... 11 General Description .......................................................................
PAGE 3
Data Sheet AD1974 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3.3 V Temperature Range 1 As specified in Table 1 and Table 2 Master Clock 12.288 MHz (48 kHz fS, 256 × fS mode) Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.
PAGE 4
AD1974 Data Sheet Specifications measured at 125°C (case). Table 2. Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Full-Scale Input Voltage (Differential) Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) Total Harmonic Distortion + Noise (THD + N) Gain Error Interchannel Gain Mismatch Offset Error REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Conditions Min All ADCs Typ Max Unit 24 1.
PAGE 5
Data Sheet AD1974 POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Digital Current Normal Operation Power-Down Analog Current Normal Operation Power-Down DISSIPATION Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Conditions/Comments Min Typ Max Unit DVDD AVDD MCLK = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz 3.0 3.0 3.3 3.3 3.6 3.6 V V 56 65 95 2.
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AD1974 Parameter PLL Lock Time 256 fS VCO Clock Output Duty Cycle MCLK_O Pin SPI PORT tCCH tCCL fCCLK tCDS tCDH tCLS tCLH tCLHIGH tCOE tCOD tCOH tCOTS ADC SERIAL PORT tABH tABL tALS tALH tALS tABDD AUXILIARY INTERFACE tXDS tXDH tXBH tXBL tXLS tXLH Data Sheet Condition Comments Min Max Unit 40 10 60 ms % 10 ns ns MHz MCLK and LRCLK input See Figure 5 CCLK high CCLK low CCLK frequency CDATA setup CDATA hold Setup Hold High COUT enable COUT delay COUT hold COUT tristate ABCLK high ABCLK low ALRCLK
PAGE 7
Data Sheet AD1974 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 8
AD1974 Data Sheet AVDD 41 CM 42 ADC1LN 43 ADC1LP 44 ADC1RP 45 ADC2LP ADC2LN 46 ADC1RN ADC2RN 47 ADC2RP AVDD 48 40 39 38 37 1 36 AGND MCLKI/XI 2 35 FILTR MCLKO/XO 3 34 AGND AGND 4 33 AVDD AVDD 5 AD1974 32 AGND NC 6 NC TOP VIEW (Not to Scale) 7 NC 8 29 NC NC 9 28 NC PD/RST 10 27 CLATCH SINGLE-ENDED OUTPUT 31 NC 30 NC 17 18 19 20 21 22 23 24 ASDATA1 ABCLK ALRCLK CIN COUT 16 ASDATA2 15 AUXBCLK 14 AUXLRCLK DVDD 13 NC CCLK DGND
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Data Sheet Pin No. 44 45 46 47 1 AD1974 Type 1 I I I O Mnemonic ADC2LN ADC2RP ADC2RN LF Description ADC2 Left Negative Input. ADC2 Right Positive Input. ADC2 Right Negative Input. PLL Loop Filter, Return to AVDD. I = input, O = output. Rev.
PAGE 10
AD1974 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 0.06 –20 0.04 –30 MAGNITUDE (dB) 0.08 0.02 0 –0.02 –40 –50 –60 –0.06 –80 –0.08 –90 –0.10 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 FREQUENCY (kHz) –100 0 5000 10000 15000 20000 25000 30000 35000 40000 FREQUENCY (kHz) Figure 4. ADC Stop-Band Filter Response, 48 kHz Figure 3. ADC Pass-Band Filter Response, 48 kHz Rev. D | Page 10 of 24 06614-003 –70 –0.04 06614-002 MAGNITUDE (dB) 0.
PAGE 11
Data Sheet AD1974 THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four ADC channels in the AD1974 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with a 79 dB stopband attenuation and a linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes).
PAGE 12
AD1974 Data Sheet Table 11. Standalone Mode Selection ADC Clocks Slave Master CIN 0 0 COUT 0 1 tCLS CLATCH 0 0 tCLH tCCH tCCL tCCP CLATCH CCLK 0 0 tCOTS CCLK tCDS tCDH COUT D23 D22 D9 tCOE D9 D8 D0 D8 D0 06614-010 CIN tCOD Figure 5. Format of the SPI Signal SERIAL CONTROL PORT The AD1974 has an SPI control port that permits programming and reading back of the internal control registers for the ADCs, DACs, and clock system.
PAGE 13
Data Sheet AD1974 The AD1974 serial ports also have several different TDM serial data modes. The first and most commonly used configuration is shown in Figure 6 where the ADC serial port outputs one data stream consisting of four on-chip ADCs followed by four unused slots. In this mode, ABCLK is set to 256 fS (8-channel TDM mode). put stream follow four on-chip ADC channel slots. It should be noted that due to the high ABCLK frequency, this mode is available only in the 48 kHz/44.
PAGE 14
AD1974 Data Sheet ALRCLK ABCLK ASDATA1 (TDM_OUT) FOUR-ON-CHIP ADC CHANNELS ADCL1 ADCR1 ADCL2 AUXILIARY ADC CHANNELS ADCR2 AUXL1 AUXR1 AUXL2 UNUSED SLOTS AUXR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED 32 BITS MSB AUXLRCLK (AUX PORT) LEFT RIGHT AUXDATA1 (AUX1_IN) MSB MSB AUXDATA2 (AUX2_IN) MSB MSB 06614-052 AUXBCLK (AUX PORT) Figure 8. 16-Channel AUX ADC Mode AD1974 must be grounded in all modes of operation.
PAGE 15
Data Sheet AD1974 ALRCLK ABCLK ASDATA1 (TDM_OUT OF THE SECOND AD1974 IN THE CHAIN) ASDATA2 (TDM_IN OF THE SECOND AD1974 IN THE CHAIN) FOUR ADC CHANNELS OF THE SECOND IC IN THE CHAIN FOUR ADC CHANNELS OF THE FIRST IC IN THE CHAIN ADCL1 ADCR1 ADCL2 ADCR2 ADCL1 ADCR1 ADCL2 ADCR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED ADCL1 ADCR1 ADCL2 ADCR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED 32 BITS SECOND AD1974 DSP 06614-057 FIRST AD197
PAGE 16
AD1974 Data Sheet tXBH AUXBCLK tXBL tXLH tXLS AUXRCLK tXDS AUXDATA LEFT JUSTIFIED MODE MSB MSB–1 tXDH tXDS AUXDATA I2S JUSTIFIED MODE MSB tXDH tXDS MSB LSB tXDH tXDH 06614-014 tXDS AUXDATA RIGHT JUSTIFIED MODE Figure 12. Auxiliary Serial Timing tABH ABCLK tABL tALH tALS ALRCLK tABDD ASDATA LEFT JUSTIFIED MODE MSB MSB–1 tABDD ASDATA I2S JUSTIFIED MODE MSB ASDATA RIGHT JUSTIFIED MODE MSB LSB 06614-015 tABDD Figure 13. ADC Serial Timing Table 13.
PAGE 17
Data Sheet AD1974 SHARC IS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN) TxCLK TFS (NC) RxDATA SHARC RxCLK 12.288MHz FSYNC-TDM (RFS) 30MHz LRCLK AUX ADC 1 BCLK DATA ASDATA1 ALRCLK ABCLK MCLK AUXLRCLK AD1974 BCLK AUXDATA1 DATA AUXDATA2 TDM MASTER AUX MASTER MCLK MCLK LRCLK AUX ADC 2 06614-019 AUXBCLK Figure 14. Example of AUX Mode Connection to SHARC® (AD1974 as TDM Master/AUX Master Shown) Rev.
PAGE 18
AD1974 Data Sheet CONTROL REGISTERS The global address for the AD1974 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Bit Global Address R/W Register Address Data 23:17 16 15:8 7:0 Table 15.
PAGE 19
Data Sheet AD1974 Table 17. PLL and Clock Control 1 Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description AUXPORT clock source select ADC clock source select On-chip voltage reference PLL lock indicator (read only) AUXPORT CONTROL REGISTERS Table 18. AUXPORT Control 0 Bit 0 2:1 5:3 7:6 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Reserved Reserved 32 kHz/44.1 kHz/48 kHz 64 kHz/88.
PAGE 20
AD1974 Data Sheet Table 20. AUXPORT Control 2 Bit 0 2:1 4:3 5 7:6 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Reserved Reserved Reserved Reserved Reserved Reserved 24 20 Reserved 16 Reserved Reserved Reserved Description Word width ADC CONTROL REGISTERS Table 21. ADC Control 0 Bit 0 1 2 3 4 5 7:6 Value 0 1 0 1 0 1 0 1 0 1 0 1 00 01 10 11 Function Normal Power down Off On Unmute Mute Unmute Mute Unmute Mute Unmute Mute 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.
PAGE 21
Data Sheet Bit 6:5 7 AD1974 Value 00 01 10 11 0 1 Function Stereo TDM (daisy chain) ADC AUX mode (TDM-coupled) Reserved Latch in midcycle (normal) Latch in at end of cycle (pipeline) Description Serial format BCLK active edge (TDM_IN) Table 23.
PAGE 22
AD1974 Data Sheet ALRCLK ABCLK ASDATA1 06614-060 DATA MUST BE VALID AT THIS BCLK EDGE MSB Figure 16. I2S Pipeline Mode in ADC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission) Rev.
PAGE 23
Data Sheet AD1974 APPLICATION CIRCUITS Typical applications circuits are shown in Figure 17 and Figure 18. Figure 17 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure 18. 120pF 100pF 5.76kΩ 2 3 + – OP275 AVDD2 4.7µF 237Ω + 120pF 1nF NP0 5 – + 5.6nF 390pF 7 4.7µF 237Ω 1nF NP0 + ADCxP 562Ω AVDD2 Figure 18. Recommended Loop Filters for LRCLK or MCLK PLL Reference ADCxN 100pF 5.76kΩ MCLK 2.2nF 3.
PAGE 24
AD1974 Data Sheet OUTLINE DIMENSIONS 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE VIEW A (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 0.75 0.60 0.45 Figure 19.