User`s manual

44
DRAM Clock/Drive Control
Scroll to this item and press <Enter> to view the following
screen:
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
DRAM Clock/Drive Control
Item Help
Current FSB Frequency
Current DRAM Frequency
DRAM Clock [100 MHz]
DRAM Timing [By SPD]
x SDRAM Cycle Length 3
x Bank Interleave Disabled
DRAM Command Rate [2T Command]
Menu Level
↑
↑↑
↑ ↓
↓↓
↓ →
→→
→ ←
←←
←
: Move Enter : Select +/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Current FSB Frequency
This item displays the frontside bus (FSB) frequency. This is a
display-only item. You cannot make changes to this field.
Current DRAM Frequency
This item displays the memory (DRAM) frequency. This is a
display-only item. You cannot make changes to this field.
DRAM Clock (100 MHz)
This item enables you to manually set the DRAM Clock. We
recommend that you leave this item at the default value.
DRAM Timing (By SPD)
Set this to the default value to enable the system to automati-
cally set the SDRAM timing by SPD (Serial Presence Detect).
SPD is an EEPROM chip on the DIMM module that stores in-
formation about the memory chips it contains, including size,
speed, voltage, row and column addresses, and manufacturer.
If you disable this item, you can use the following three items
to manually set the timing parameters for the system memory
SDRAM Cycle Length (3)
When synchronous DRAM is installed, the number of clock