User's Manual

MaxID RM100 RFID reader interface
Project - RFID ID1170 Version 0.1 18 October, 2005 Page 21 of 24
8. Description
8.1 RFID Reader
The Reader can be divided into two sections namely:
1) Receiver and
2) Transmitter
Both the receiver and transmitter share a local oscillator drive to ensure that all
signals are in phase with each other. The synthesiser is programmed by the CPU
to hop between 902 and 928 MHz. The Synthesizer incorporates a phase lock
loop as well as a local oscillator, with an output of –5dBm.
This local oscillator frequency is then amplified by 15dB and then fed to a in-phase
splitter. The splitter provides a +7dBm drive to the receiver board as well as to the
transmitter main amplifier. The amplifier has 2 functions:
1) Amplify the RF signal to +30.5dBm
2) Act as an AM modulator by switching between two power levels.
The PA has 2 bias inputs, One is used to adjust output power levels and the other
is used to change the AM modulation index
Lastly the PA output is fed via a harmonic low pass filter to the antenna connector.
On the receiver circuit, the RF input is fed via a 902-928 band pass filter to the
direct IQ demodulator. The demodulator uses the local oscillator to directly convert
the received signals to base band signals.
The demodulator outputs Q and I base band signals. These signals are then fed to
a 500 KHz low pass filter and 2-stage amplifier. These signals are then passed to
a differential Analogue to Digital converter and then passed on to a FPGA. The
FPGA use peak and level detection to filter out tag data and then pass the
received tag data to a 16bit processor.
The processor is responsible for the following:
1) RS232 interface to host
2) Channel selection and frequency hopping
3) Reader to tag modulation
4) Transmitter power levels
5) Tag data decoding and CRC checking