Datasheet

71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 53 of 104
A Maxim Integrated Products Brand
Figure 18: MPU/CE Communication (Functional)
The MPU will wait for the CE to signal that fresh data is ready (the XFER interrupt). It will read the data and perform additional
processing such as energy accumulation.
Figure 19: MPU/CE Communication (Processing Sequence)
Fault, Reset, Power-Up
Reset Mode: When the RESETZ pin is pulled low or when V1 < VBIAS, all digital activity in the chip stops while analog circuits
are still active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared. As long as V1, the
input voltage at the power fault block, is greater than VBIAS, the internal 2.5V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100
cycles of the real time clock after RESETZ goes high, at which time the MPU will begin executing its preboot and boot
sequences from address 00. See the security section for more description of preboot and boot.
I/O RAM (CONFIGURATION RAM)
MPU
CE
PULSES
DATA
INTERRUPTS
DISPLAY (me-
mory-mapped
LCD segments)
DIO
EEPROM
(I2C)
SERIAL
(UART0/1)
SAMPLES
APULSEW
APULSER
VAR (DIO7) W (DIO6)
VARSUM
WSUM
ADC
EXT_PULSE
CE_BUSY
XFER_BUSY
Mux Ctrl.
CE_EN
CE PRAM
COMPUTATION
ENGINE
CE DRAM
FLASH
MPU
XFER Interrupt