Datasheet

71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 63 of 104
A Maxim Integrated Products Brand
Name
Location
[Bit(s)]
Dir Description
FLSH_PGADR SFR
B7[7:1]
W Flash Page Erase Address
FLSH_PGADR[6:0] –
Flash Page Address (page 0 thru 127) that will be
erased during the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
FLSH_PWE SFR B2[0] R/W Program Write Enable
0 – MOVX commands refer to XRAM Space, normal operation (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this
bit are inhibited when interrupts are enabled.
IE_XFER
IE_RTC
SFR E8[0]
SFR E8[1]
R/W Interrupt flags. These flags are part of the WDI SFR register and monitor the
XFER_BUSY interrupt and the RTC_1SEC inter
rupt. The flags are set by
hardware and must be cleared by the interrupt handler. See also WD_RST.
INTBITS SFR
F8[6:0]
R Interrupt
inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any memory and
are primarily intended for debug use.
LCD_BSTEN
2020[7]
R/W
Enables the LCD voltage boost circuit.
LCD_CLK[1:0]
2021[1:0] R/W
Sets the LCD clock frequency for COM/SEG pins (not the frame rate. Note:
f
w
= CKFIR/128
00: f
w
/2
9
, 01: f
w
/2
8
, 10: f
w
/2
7
, 11: f
w
/2
6
LCD_EN
2021[5] R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs.
LCD_FS[4:0] 2022[4:0] R/W Controls the LCD full scale voltage, VLC2:
)
31
_
3.07.0(
2
FSLCD
VLCDVLC +⋅=
LCD_MODE[2:0] 2021[4:2] R/W The LCD bias mode.
000: 4 states, 1/3 bias
001: 3 states, 1/3 bias
010: 2 states, ½ bias
011: 3 states, ½ bias
100: static display