Energy Meter IC Family Software Instruction Manual

71M652X Software User’s Guide

Revision 1.7 TERIDIAN Proprietary 127 of 138

Refreshing the WD Timer

The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This re-

quirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the

second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this

period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded

with the content of the WDTREL register and WDT is automatically reset.

Special Function Registers for the WD Timer

Interrupt Enable 0 Register (IEN0):

MSB LSB

EALl WDT ET2 ES0 ET1 EX1 ET0 EX0

Table 6-33: The IEN0 Register

Bit Symbol Function

IEN0.6 WDT Watchdog timer refresh flag.

Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is

set to prevent an unintentional refresh of the watchdog timer. WDT is reset by

hardware 12 clock cycles after it has been set.

Table 6-34: The IEN0 Bit Functions

Note: The remaining bits in the IEN0 register are not used for watchdog control

Interrupt Enable 1 Register (IEN1):

MSB LSB

EXEN2 SWDT EX6 EX5 EX4 EX3 EX2

Table 6-35: The IEN1 Register

Bit Symbol Function

IEN1.6 SWDT Watchdog timer start/refresh flag.

Set to activate/refresh the watchdog timer. When directly set after setting WDT, a

watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock

cycles after it has been set.

Table 6-36: The IEN1 Bit Functions

Note: The remaining bits in the IEN1 register are not used for watchdog control

Interrupt Priority 0 Register (IP0):

MSB LSB

OWDS WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Table 6-37: The IP0 Register

Bit Symbol Function