Energy Meter IC Family Software Instruction Manual

71M652X Software User’s Guide
Revision 1.7 TERIDIAN Proprietary 50 of 138
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
5.4.2 Foreground
There are total 12 interrupts available for the 80515, and the revision 4.7a Demo Code uses a total of 11 interrupts.
Table 5-10 shows the interrupt service routines (ISRs), the corresponding vectors (T
able 6-58 in section 6.3.5.4) and
their priority, as assigned by the MPU using the IP0 and IP1 registers (see section 6.3.5.2).
Interrupt Source Interrupt Service
Routine
External or
Internal
Interrupt
In source file Vector Priority
(3 =
highest)
Pulse count pcnt_w_isr() EXT0 pcnt.c 0x03 0
Pulse count pcnt_v_isr() EXT1 pcnt.c 0x13 3
Flash-Write collision
fwcol0
fwcol_isr() EXT2 flash.c 0x4B 0
Flash-Write collision
fwcol1
fwcol_isr() EXT2 flash.c 0x4B 0
CE Busy ce_busyz_int() EXT3 ce.c 0x53 3
Power fail/power return pll_isr() EXT4 batmodes_20.c 0x5B 3
EEPROM eeprom_isr() EXT5 eeprom.c 0x63 0
XFER busy ce_xfer_busyz_rtc_int() EXT6 (shared
w/ RTC)
ce.c 0x6B 2
RTC rtc_isr() EXT6 (shared
w/ XFER)
rtc.c 0x6B 2
Timer0 tmr0_isr() tmr0.c 0x0B 0
Timer1 tmr1_isr() tmr1.c 0x1B 3
UART 0 es0_isr serial.c 0x23 0
UART 1 es1_isr serial.c 0x83 0
Table 5-10: Interrupt Service Routines
In general, a higher priority interrupt can preempt lower-priority interrupt code. The interrupt priority hardware is
controlled by two registers, IP and IP1 (named IPL and IPH in the demo code). The MPU supports four priorities, and a
fifth is possible with a small amount of software support.
The best practice is to set priorities once, near the start of initialization. Setting priorities dynamically while interrupts
occur can have undefined results. Since some of the interrupts detect power failures that can occur at any time,
changing interrupt priorities in the middle of the code is not recommended.
In the 6521 demo code, interrupt priorities are set higher for urgent tasks. Among equally-urgent tasks, priorities are set
higher for faster interrupts. The following describes interrupt priorities for the version 4.3.3 of the Demo Code:
The priority is set once, in main_init() of main\Main.c. It is also cleared to 0s in the soft reset routine, but this is followed
by logic that calls four RTIs to reset the interrupt acknowledge logic for all four hardware interrupt levels. The system
priority value is assembled from constants in Main\options_gbl.h. The constants are defined in Util\priority2x.h.
The highest priority interrupt group are the PLL_OK interrupt (external interrupt 4, see Main\batmodes_20.c), and timer
1. PLL_OK is urgent because it indicates power supply failure, and the software must start battery modes. Timer 1
shares the same priority bits, and is currently unused (sample code is in Io\tmr1.c, &.h), though earlier versions used it
to set the real-time-clock.
The high-priority interrupt group is used for CE_BUSY (external interrupt 3, see Meter\ce.c), pulse counting (external
interrupts 0 and 1, Meter\pcnt.c) and Serial 1 (Io\ser1.c&.h). External interrupt 3 and 1 share priority bits, as does
external interrupt 0 and serial 1. CE_BUSY is urgent because it occasionally reads the CE's status to detect sag. The
pulse counting interrupts are less urgent, but they are small and run very quickly. Serial 1 is intended for AMR, so
making its interrupts high priority should help its data transfer timing to be more reliable.
The low priority group contains Serial 0 and Timer 0. These can generally wait a millisecond, and if necessary, can
afford to miss fast interrupts. Serial 0 is the command line interface (See the directory Cli), and Timer 0 is run at a 10
millisecond interval as the timebase for the software timers (Util\tmr.c, Io\tmr0.c&.h). Serial 0 shares its priority bits with