Energy Meter IC Family Software Instruction Manual

71M652X Software User’s Guide
Revision 1.7 TERIDIAN Proprietary 98 of 138
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
The demo software is designed so that the serial port always runs at 300 bd, in both mission mode and brownout
mode. The 6521 has special clock-interpolation logic in the baud rate generation so that 300 baud works in brownout
mode. The designers chose this 300 bd especially because it is compatible with some AMR applications, such as
FLAG, and it was achievable in the chip. The Demo Code tests for brownout mode, and sets the 300 bd values in the
serial ports’ bd rate generator in this case.
In brownout mode, the code runs 150 times slower than in mission mode, and it can easily fail to reset the watchdog.
The Demo Code arranges to reset the watchdog from both the main loop and the RTC’s 1-second interrupt, which has
unchanged timing. It uses a “software watchdog” scheme to try to keep this respectable. The idea is that as soon as all
the needed places have called the watchdog routine, the hardware watchdog is reset.
Code for brownout mode should minimize calculations, because brownout mode is 150 times slower than mission
mode. To minimize the calculations, in the Demo Code, every accumulation interval in mission mode caches a pre-
calculated Wh value for use in a transition to brownout mode. When the interrupt for brownout mode executes, this
value is converted to the digits of the LCD registers. The LCD registers are nonvolatile in sleep and LCD modes, so
they are not lost in any battery-mode transitions. Later, when the Demo Code awakes (probably because the push-
button was pressed) in brownout mode, it runs through the brief initialization needed by the C environment, and in
main(), it tests for brownout mode. In the brownout mode’s code it runs a very simple, fast state machine that uses the
wake button flag to decide whether to enter sleep mode or LCD mode, and just depends on the LCD registers to
remain unchanged.
An algorithm similar to this could be adapted to display several values, setting the new value in the LCD as the last
step after all other calculations were done in brownout mode. After displaying the values in the LCD, the code could
enter LCD mode to save power and still display the value.
When the chip wakes from sleep or LCD mode, the PC is cleared to zero, and the I/O bits that are not needed for the
RTC or LCD are reset. The experience of the firmware designers is that it is most convenient to treat transitions from
LCD and sleep modes like resets. This permits a relatively simple start-up initialization to handle the state-transitions,
as well as power-up in mission mode. That scheme proved so convenient that the Demo Code also used the same
scheme to transition to and from brownout mode.
It’s not clear at first how to distinguish hard resets from battery-mode transitions. The code can use the nonvolatile LCD
control registers. The trick is that after a reset, the LCD registers are cleared. In particular, LCD_NUM, bits 0..4 of
XDATA address 0x2020 are cleared after a hard reset.
5.17.4 Three-Wire EEPROM Hardware
The 71M6521 includes a new three-wire serial EEPROM interface, which is designed to be compatible with
MicroWire™ EEPROMs.
The new 3-wire interface hardware is very fast, transferring a byte in only 16µs. This high speed has made it relatively
uneconomical to use the interrupt provided on this interface. At 16µs per byte, the interrupt overhead would be most of
the delay in the EEPROM control firmware. Therefore, the Demo Code uses a polling driver that reads the ready bit.
Some 3-wire serial EEPROMs (e.g. the Microchip 93C76C) signal completion of a write operation by driving the data
line from low to high. The 71M6521 handles this with two controls: First, there is a “HIZ” bit in EECTRL that forces the
output of the 71M6521 to a high-impedance state after the last bit is sent. Also, the bit WFR (wait for ready) in EECTRL
makes the 71M6521’s BUSY status bit stay true until the data line becomes high. However, there is a period during
which the data line is not driven. If the data line is not pulled-down, a trailing 1 on the last data bit will leave the line
capacitance holding the line well above the transition voltage, causing BUSY to become prematurely false. But if the
pull-down is too powerful, the EEPROM may not be able to drive it (e.g. the 93C76C has only 400µA of drive on the
high state of the data line). An alternative method (uwreep.c in the Demo Code) that is clumsy but reliable and
inexpensive (it saves the resistor), is to complete the last data write without any special modes, then send another 8
bits of zero, with the wait-for-ready and high-Z bits set for that transfer. Note that sending one bit of zero works in
simulations, but not in the lab, for reasons that are not yet clear.
The demo source code also includes a programmed-IO (bit-banging) driver (uwrdio.c). This driver lets 71M6511 and
71M6513 chips use 3-wire EEPROMs, so meter product-lines can share an inventory of identical EEPROMs. Also, the
71M6521’s 3-wire interface hardware is not flexible enough to drive some items designed for SPI. It only supports one
clock polarity, one clock edge and the data line is half duplex. The programmed-IO driver is designed to be easily
modified for these environments.