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71M6521DE/DH/FE

Energy Meter ICs

DATA SHEET

Rev 3 Page: 1 of 107

19-5370; Rev 3; 7/12

GENERAL DESCRIPTION

The Teridian™ 71M6521DE/DH/FE energy meter ICs are highly integrated

systems-on-a-chip (SoCs) with an MPU core, RTC, flash, and LCD driver.

The Single Converter Technology® with a 22-bit delta-sigma ADC, four

analog inputs, digital temperature compensation, precision voltage

reference, battery voltage monitor, and 32-bit computation engine (CE)

supports a wide range of residential metering applications with very few

low-cost external components. A 32kHz crystal time base for the entire

system and internal battery-backup support for RAM and RTC further

reduce system cost. The ICs support 2-wire, 3-wire, and 4-wire single-

phase and dual-phase residential metering along with tamper-detection

mechanisms.

Maximum design flexibility is provided by multiple UARTs, I

MICROWIRE®, up to 18 DIO pins, and in-system programmable flash

memory, which can be updated with data or application code in operation.

A complete array of ICE and development tools, programming libraries, and

reference designs enable rapid development and certification of TOU,

AMR, and prepay meters that comply with worldwide electricity metering

standards.

FEATURES

• Up to 0.1% Wh Accuracy Over 2000:1 Current

Range

• Exceeds IEC 62053/ANSI C 12.20 Standards

• Voltage Reference < 40 ppm/°C (< 20ppm/°C for

71M6521DH)

• Four Sensor Inputs—V

Referenced

• Low-Jitter Wh and VARh Pulse Test Outputs

(10kHz max)

• Pulse Count for Pulse Outputs

• Four-Quadrant Metering

• Tamper Detection

Neutral Current with CT or Shunt

• Line Frequency Count for RTC

• Digital Temperature Compensation

• Sag Detection for Phase A and B

• Independent 32-Bit Compute Engine

• 46-64Hz Line Frequency Range with Same

Calibration

• Phase Compensation (±7°)

• Battery backup for RTC and battery monitor

• Three Battery Modes with Wake-Up on Pushbutton

or Timer:

Brownout Mode (48µA)

LCD Mode (5.7µA)

Sleep Mode (2.9µA)

• Energy Display on Main Power Failure

• Wake-Up with Pushbutton

• 22-Bit Delta-Sigma ADC

• 8-Bit MPU (80515), 1 Clock Cycle per Instruction

with Integrated ICE for MPU Debug

• RTC with Temperature Compensation

• Auto-Calibration

• Hardware Watchdog Timer, Power-Fail Monitor

• LCD Driver (Up to 152 Pixels)

• Up to 18 General-Purpose I/O Pins

• 32kHz Time Base

• 16KB (6521DE/DH) or 32KB (6521FE) Flash with

Security

• 2KB MPU XRAM

• Two UARTs for IR and AMR

• Digital I/O Pins Compatible with 5V Inputs

• 64-Pin LQFP or 68-Pin QFN Package

• Lead(Pb)-Free Packages

MPU

RTC

TIMERS

XIN

XOUT

VREF

RX/DIO1

TX/DIO2

COM0..3

V3.3A

V3.3

SYS

VBAT

V2.5

VBIAS

SEG0..18

GNDA GNDD

SEG 24..31/

DIO 4..11

SEG 34..37/

DIO 14..17

ICE

LOAD

88.88.8888

IIC or uWire

EEPROM

POWER

FAULT

AMR

TEST PULSES

COMPARATOR

SENSE

DRIVE/MOD

SERIAL PORTS

OSC/PLL

CONVERTER

DIO, PULSE

COMPUTE

ENGINE

FLASH

RAM

VOLTAGE REF

REGULATOR

POWER SUPPLY

TERIDIAN

71M6521

3.3V LCD

TEMP

SENSOR

32 kHz

NEUT

CT/SHUNT

07/25/2007

LOAD

PWR MODE

CONTROL

WAKE-UP

BATTERY

ICE_E GNDD

V3P3D

SEG 32,33,

38/ICE

Teridian is a trademark and Single Converter Technology is a registered

trademark of Maxim Integrated Products Inc.

MICROWIRE is a registered trademark of National Semiconductor Corp.

Summary of content (107 pages)

PAGE 1
9-5370; Rev 3; 7/12 71M6521DE/DH/FE Energy Meter ICs DATA SHEET FEATURES GENERAL DESCRIPTION The Teridian™ 71M6521DE/DH/FE energy meter ICs are highly integrated systems-on-a-chip (SoCs) with an MPU core, RTC, flash, and LCD driver.
PAGE 2
71M6521DE/DH/FE Data Sheet Table of Contents GENERAL DESCRIPTION ........................................................................................................................ 1 FEATURES ................................................................................................................................................ 1 HARDWARE DESCRIPTION ..................................................................................................................... 10 Hardware Overview .......
PAGE 3
71M6521DE/DH/FE Data Sheet Hardware Watchdog Timer ............................................................................................ 46 Program Security ........................................................................................................... 46 Test Ports ...................................................................................................................... 47 FUNCTIONAL DESCRIPTION .................................................................................
PAGE 4
71M6521DE/DH/FE Data Sheet Formats ......................................................................................................................... 82 Constants ...................................................................................................................... 82 Environment .................................................................................................................. 82 CE Calculations ..........................................................................
PAGE 5
71M6521DE/DH/FE Data Sheet ORDERING INFORMATION ...................................................................................................................... 105 REVISION HISTORY .................................................................................................................................
PAGE 6
71M6521DE/DH/FE Data Sheet List of Figures Figure 1: IC Functional Block Diagram ....................................................................................................................................9 Figure 2: General Topology of a Chopped Amplifier .............................................................................................................11 Figure 3: AFE Block Diagram...........................................................................................................
PAGE 7
1M6521DE/DH/FE Data Sheet List of Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ..................................................................................11 Table 2: CE DRAM Locations for ADC Results......................................................................................................................14 Table 3: Meter Equations. ..............................................................................................................................
PAGE 8
71M6521DE/DH/FE Data Sheet Table 55: DIO_DIR Control Bit ............................................................................................................................................41 Table 56: Selectable Controls using the DIO_DIR Bits ........................................................................................................42 Table 57: EECTRL Status Bits ...........................................................................................................................
PAGE 9
71M6521DE/DH/FE Data Sheet V3P3A VREF IA VA IB VB ∆Σ ADC CONVERTER VBAT V3P3D - V3P3A VREF TEMP MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV X4MHZ ADC_E VOLT REG MCK PLL RTCLK (32KHz) DIV ADC CK32 32KHz GNDD LCD_ONLY SLEEP CKADC CKOUT_E 4.9MHz CKOUT_E V2P5 CKFIR 4.9MHz 4.9MHz CK_GEN V3P3D CK_2X MUX_SYNC WPULSE VARPULSE STRT CE TEST MODE LCD DISPLAY DRIVER MEMORY SHARE 1000-11FF RTM_0..
PAGE 10
71M6521DE/DH/FE Data Sheet HARDWARE DESCRIPTION Hardware Overview The Teridian 71M6521DE/DH/FE single-chip energy meter integrates all primary functional blocks required to implement a solid-state electricity meter.
PAGE 11
71M6521DE/DH/FE Data Sheet Regular MUX Sequence Mux State 0 1 2 3 IA VA IB VB EQU 0, 1, 2 ALT MUX Sequence Mux State 0 1 2 TEMP VA VBAT 3 VB Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles In a typical application, IA and IB are connected to current transformers that sense the current on each phase of the line voltage. VA and VB are typically connected to voltage sensors through resistor dividers. The multiplexer control circuit handles the setting of the multiplexer.
PAGE 12
71M6521DE/DH/FE Data Sheet It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS in the “A” position, the output voltage is: Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff With all switches set to the “B” position by applying the inverted CROSS signal, the output voltage is: Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or Voutp – Voutn = G (Vinp – Vinn) - G Voff Thus, when CROSS is toggled, e.g.
PAGE 13
71M6521DE/DH/FE Data Sheet Battery Monitor The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45kΩ load resistor is applied to the battery, and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 07.
PAGE 14
71M6521DE/DH/FE Data Sheet The CE DRAM contains 128 32-bit words. The MPU can read and write the CE DRAM as the primary means of data communication between the two processors. Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.
PAGE 15
71M6521DE/DH/FE Data Sheet Real-Time Monitor The CE contains a Real-Time Monitor (RTM), which can be programmed through the UART to monitor four selectable CE DRAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit.
PAGE 16
71M6521DE/DH/FE Data Sheet 1/32768Hz = 30.518µs IB VB IA VA 13/32768Hz = 397µs per mux cycle Figure 4: Samples from Multiplexer Cycle The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
PAGE 17
71M6521DE/DH/FE Data Sheet 80515 MPU Core The 71M6521DE/DH/FE includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 5 MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single cycle.
PAGE 18
71M6521DE/DH/FE Data Sheet CKCON register CKCON.2 Stretch Value Read signals width Write signal width CKCON.1 CKCON.
PAGE 19
71M6521DE/DH/FE Data Sheet Internal Data Memory: The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 6 shows the internal data memory map.
PAGE 20
71M6521DE/DH/FE Data Sheet Special Function Registers (Generic 80515 SFRs) Table 8 shows the location of the SFRs and the value they assume at reset or power-up.
PAGE 21
71M6521DE/DH/FE Data Sheet Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC. B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. Program Status Word (PSW): MSB LSB CV AC F0 RS1 RS OV - P Table 9: PSW Register Flags Bit Symbol Function PSW.
PAGE 22
71M6521DE/DH/FE Data Sheet SFR Address R/W Description P0 DIR0 0x80 0xA2 R/W R/W P1 DIR1 P2 DIR2 0x90 0x91 0xA0 0xA1 R/W R/W R/W R/W Register for port 0 read and write operations (pins DIO4…DIO7) Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is an output. Register for port 1 read and write operations (pins DIO8…DIO11, DIO14-DIO15) Data direction register for port 1.
PAGE 23
71M6521DE/DH/FE Data Sheet FLSHCRL 0xB2 R/W W R/W R WDI 0xE8 R/W R/W W INTBITS INT0…INT6 0xF8 R Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer to XRAM Space, normal operation (default). 1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. Bit 1 (FLSH_MEEN): Mass Erase Enable: 0 – Mass Erase disabled (default). 1 – Mass Erase enabled.
PAGE 24
71M6521DE/DH/FE Data Sheet Using Timer 1 Using Internal Baud Rate Generator UART 0 2smod * fCKMPU/ (384 * (256-TH1)) 2smod * fCKMPU/(64 * (210-S0REL)) UART 1 N/A fCKMPU/(32 * (210-S1REL)) Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the SMOD bit in the SFR PCON. TH1 is the high byte of timer 1.
PAGE 25
71M6521DE/DH/FE Data Sheet MSB LSB SM - SM21 REN1 TB81 RB81 TI1 RI1 Table 16: The S1CON register Bit Symbol S0CON.7 SM0 S0CON.6 Function These two bits set the UART0 mode: SM0 Mode Description 0 N/A 0 SM1 SM1 0 1 8-bit UART 0 1 2 9-bit UART 1 0 3 9-bit UART 1 1 S0CON.5 SM20 Enables the inter-processor communication feature. S0CON.4 REN0 If set, enables serial reception. Cleared by software to disable reception. S0CON.3 TB80 The 9th transmitted data bit in Modes 2 and 3.
PAGE 26
71M6521DE/DH/FE Data Sheet In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency.
PAGE 27
71M6521DE/DH/FE Data Sheet Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode. Timer/Counter Mode Control register (TMOD): MSB LSB GATE C/T M1 Timer 1 M0 GATE C/T M1 Timer 0 M0 Table 21: The TMOD Register Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 19 and Table 20) start their associated timers when set. Bit Symbol Function TMOD.7 TMOD.
PAGE 28
71M6521DE/DH/FE Data Sheet Table 24 specifies the combinations of operation modes allowed for timer 0 and timer 1: Timer 1 Timer 0 - mode 0 Mode 0 Mode 1 Mode 2 YES YES YES Timer 0 - mode 1 YES YES YES Timer 0 - mode 2 Not allowed Not allowed YES Table 24: Timer Modes Timer/Counter Mode Control register (PCON): MSB LSB SMOD -- -- -- -- -- -- -- Table 25: The PCON Register The SMOD bit in the PCON register doubles the baud rate when set. Bit Symbol PCON.
PAGE 29
71M6521DE/DH/FE Data Sheet Special Function Registers for the WD Timer Interrupt Enable 0 Register (IEN0): MSB LSB EAL WDT ET2 ES0 ET1 EX1 ET0 EX0 Table 27: The IEN0 Register (see also Table 32) Bit Symbol IEN0.6 WDT Function Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by hardware 12 clock cycles after it has been set.
PAGE 30
71M6521DE/DH/FE Data Sheet Bit Symbol IP0.6 WDTS Function Watchdog timer status flag. Set when the watchdog timer was started. Can be read by software. Table 32: The IP0 bit Functions (see also Table 45) Note: The remaining bits in the IP0 register are not used for watchdog control Watchdog Timer Reload Register (WDTREL): MSB LSB 7 6 5 4 3 2 1 0 Table 33: The WDTREL Register Bit Symbol Function WDTREL.7 7 Prescaler select bit.
PAGE 31
71M6521DE/DH/FE Data Sheet On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions are met: • • • No interrupt of equal or higher priority is already in progress. An instruction is currently being executed and is not completed. The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
PAGE 32
71M6521DE/DH/FE Data Sheet Interrupt Enable 2 register (IE2) MSB LSB - - - - - - - ES1 Table 39: The IEN2 Register Bit Symbol IEN2.0 ES1 Function ES1=0 – disable serial channel 1 interrupt Table 40: The IEN2 Bit Functions Timer/Counter Control register (TCON) MSB LSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Table 41: The TCON Register Bit Symbol Function TCON.7 TF1 Timer 1 overflow flag TCON.6 TR1 Not used for interrupt control TCON.5 TF0 Timer 0 overflow flag TCON.
PAGE 33
71M6521DE/DH/FE Data Sheet Interrupt Request register (IRCON) MSB LSB EX6 IEX5 IEX4 IEX3 IEX2 Table 44: The IRCON Register Bit Symbol Function IRCON.7 - IRCON.6 - IRCON.5 IEX6 External interrupt 6 edge flag IRCON.4 IEX5 External interrupt 5 edge flag IRCON.3 IEX4 External interrupt 4 edge flag IRCON.2 IEX3 External interrupt 3 edge flag IRCON.1 IEX2 External interrupt 2 edge flag IRCON.
PAGE 34
71M6521DE/DH/FE Data Sheet Interrupt Enable NAME LOCATION EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX_XFER EX_RTC SFR A8[[0] SFR A8[2] SFR B8[1] SFR B8[2] SFR B8[3] SFR B8[4] SFR B8[5] 2002[0] 2002[1] EX_FWCOL 2007[4] EX_PLL 2007[5] Interrupt Flag NAME LOCATION IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_XFER IE_RTC IE_FWCOL0 IE_FWCOL1 IE_PLLRISE IE_PLLFALL IE_WAKE IE_PB SFR 88[1] SFR 88[3] SFR C0[1] SFR C0[2] SFR C0[3] SFR C0[4] SFR C0[5] SFR E8[0] SFR E8[1] SFR E8[3] SFR E8[2] SFRE8[6] SFRE8[7] SFRE8[5] SFRE8[4]
PAGE 35
71M6521DE/DH/FE Data Sheet Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 48: Group 0 External interrupt 0 Serial channel 1 interrupt 1 Timer 0 interrupt - External interrupt 2 2 External interrupt 1 - External interrupt 3 3 Timer 1 interrupt - External interrupt 4 4 Serial channel 0 interrupt - External interrupt 5 5 - - External interrupt 6 Table 48: Priority Level Groups Each group of interrupt sources can be programmed individua
PAGE 36
71M6521DE/DH/FE Data Sheet External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt Polling sequence External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Table 52: Interrupt Polling Sequence Interrupt Sources and Vectors Table 53 shows the interrupts with their associated flags and vector addresses.
PAGE 37
71M6521DE/DH/FE Data Sheet Individual Interrupt Flags General Interrupt Flags Logic and Polarity Selection Interrupt Control Re g i s t e r Interrupt Enable IEN0.7 IEN0.0 Priority Assignment IE0 DIO IEN2.0 RI1 UART1 (optical) IP1.0/ IP0.0 >=1 TI1 IEN0.1 TF0 Timer 0 Flash Write Collision IEN1.1 IE_FWCOL0 IE_FWCOL1 INT2 I2FR IP1.1/ IP0.1 Polling Se quen ce Internal/ External Source Interrupt Vector IRCON.1 IEN0.2 IE1 DIO IEN1.2 INT3 CE_BUSY I3FR IP1.2/ IP0.2 IRCON.2 IEN0.
PAGE 38
71M6521DE/DH/FE Data Sheet On-Chip Resources Oscillator The 71M6521DE/DH/FE oscillator drives a standard 32.768kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The 71M6521DE/DH/FE oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. PLL and Internal Clocks Timing for the device is derived from the 32.768kHz oscillator output.
PAGE 39
71M6521DE/DH/FE Data Sheet Physical Memory Flash Memory: The 71M6521DE/DH/FE includes 16KB (71M6521DE/DH) or 32KB (71M6521FE) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program must begin on a 1KB boundary of the flash address.
PAGE 40
71M6521DE/DH/FE Data Sheet Optical Interface The device includes an interface to implement an IR/optical port. The pin OPT_Tx is designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX is designed to sense the input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated UART port (UART1). The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, respectively.
PAGE 41
71M6521DE/DH/FE Data Sheet DIO Pin no. (64 LQFP) Pin no. (68 QFN) Data Register Direction Register Internal Resources Configurable DIO Pin no. (64 LQFP) Pin no.
PAGE 42
71M6521DE/DH/FE Data Sheet 71M6521 71M6521 V3P3SYS VBAT V3P3D 3.3V V3P3SYS VBAT V3P3D 3.
PAGE 43
71M6521DE/DH/FE Data Sheet EEPROM Interface The 71M6521DE/DH/FE provides hardware support for either type of EEPROM interface, a two-pin interface and a three-pin interface. The interfaces use the EECTRL and EEDATA registers for communication. Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto pins DIO4 (SCK) and DIO5 (SDA) controlled by the DIO_EEX bit I/O RAM (see I/O RAM Table).
PAGE 44
71M6521DE/DH/FE Data Sheet Three-Wire EEPROM Interface A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with DIO_EEX=3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 58. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits.
PAGE 45
71M6521DE/DH/FE Data Sheet EECTRL Byte Written INT5 CNT Cycles (8 shown) READ SCLK (output) SDATA (input) D7 D6 SDATA output Z D5 D4 D3 D2 D1 D0 (HiZ) BUSY (bit) Figure 11: 3-Wire Interface. Read Command.
PAGE 46
71M6521DE/DH/FE Data Sheet Hardware Watchdog Timer V1 V3P3 V3P3 - 10mV WDT disabled V3P3 400mV Normal operation, WDT enabled VBIAS Battery modes 0V In addition to the basic watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, watchdog timer (WDT) is included in the device. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds.
PAGE 47
71M6521DE/DH/FE Data Sheet Test Ports TMUXOUT Pin: One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX (0x20AA[4:0]), as shown in Table 59.
PAGE 48
71M6521DE/DH/FE Data Sheet FUNCTIONAL DESCRIPTION Theory of Operation The energy delivered by a power source into a load can be expressed as: t E = ∫ V (t ) I (t )dt 0 Assuming phase angles are constant, the following formulae apply:  P = Real Energy [Wh] = V * A * cos φ* t  Q = Reactive Energy [VARh] = V * A * sin φ * t  S = Apparent Energy [VAh] = P2 + Q2 For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly.
PAGE 49
71M6521DE/DH/FE Data Sheet System Timing Summary Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output streams. In this example, MUX_DIV=4 and FIR_LEN=1 (384). The duration of each MUX frame is 1 + MUX_DIV * 2 if FIR_LEN=288, and 1 + MUX_DIV * 3 if FIR_LEN=384. An ADC conversion will always consume an integer number of CK32 clocks.
PAGE 50
71M6521DE/DH/FE Data Sheet Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1
PAGE 51
71M6521DE/DH/FE Data Sheet Circuit Function CE CE Data RAM FIR Analog circuits: PLL, ADC, VREF, BME etc MPU clock rate MPU_DIV ICE DIO Pins Watchdog Timer LCD EEPROM Interface (2-wire) EEPROM Interface (3-wire) UART Optical TX modulation Flash Read Flash Page Erase Flash Write RAM Read and Write Wakeup Timer Oscillator and RTC DRAM data preservation V3P3D voltage output pin System Power MISSION BROWNOUT LCD SLEEP Yes Yes Yes -Yes -- ---- ---- Yes -- -- -- 4.
PAGE 52
71M6521DE/DH/FE Data Sheet MISSION RESET V3P3SYS falls IE_PLLRISE -> 1 V3P3SYS rises V1 > VBIAS V1 <= VBIAS IE_PLLFALL -> 1 V3P3SYS rises LCD_ONLY BROWNOUT V3P3SYS rises IE_PB -> 1 PB RESET & VBAT_OK IE_WAKE -> 1 SLEEP or VBAT_OK timer LCD timer PB VBAT_OK VBAT_OK RESET & VBAT_OK SLEEP Figure 18: Operation Modes State Diagram LCD Mode In LCD mode, the data contained in the LCD_SEG registers is displayed, i.e.
PAGE 53
71M6521DE/DH/FE Data Sheet V3P3A VREF IA VA IB VB ∆Σ ADC CONVERTER VBAT V3P3D - V3P3A VREF TEMP MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV X4MHZ OSC (32KHz) XIN FIR ADC_E VREF VREF_CAL VREF_DIS MUX V3P3D VBIAS VBIAS MUX + VOLT REG MCK PLL RTCLK (32KHz) DIV ADC CK32 32KHz GNDD LCD_ONLY SLEEP CKADC CKOUT_E 4.9MHz CKOUT_E V2P5 CKFIR 4.9MHz 4.9MHz V3P3D CK_2X MUX_SYNC WPULSE VARPULSE STRT CE TEST MODE LCD DISPLAY DRIVER MEMORY SHARE 1000-11FF RTM_0..
PAGE 54
71M6521DE/DH/FE Data Sheet V3P3A VREF IA VA IB VB ∆Σ ADC CONVERTER VBAT V3P3D - V3P3A VREF TEMP MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV X4MHZ OSC (32KHz) XIN FIR ADC_E VREF VREF_CAL VREF_DIS MUX V3P3D VBIAS VBIAS MUX + VOLT REG MCK PLL RTCLK (32KHz) DIV ADC CK32 32KHz GNDD LCD_ONLY SLEEP CKADC CKOUT_E 4.9MHz CKOUT_E V2P5 CKFIR 4.9MHz 4.9MHz V3P3D CK_2X MUX_SYNC WPULSE VARPULSE STRT CE TEST MODE LCD DISPLAY DRIVER MEMORY SHARE 1000-11FF RTM_0..
PAGE 55
71M6521DE/DH/FE Data Sheet V3P3A VREF IA VA IB VB ∆Σ ADC CONVERTER VBAT V3P3D - V3P3A VREF TEMP MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV X4MHZ OSC (32KHz) XIN FIR ADC_E VREF VREF_CAL VREF_DIS MUX V3P3D VBIAS VBIAS MUX + VOLT REG MCK PLL RTCLK (32KHz) DIV ADC CK32 32KHz GNDD LCD_ONLY SLEEP CKADC CKOUT_E 4.9MHz CKOUT_E V2P5 CKFIR 4.9MHz 4.9MHz V3P3D CK_2X MUX_SYNC WPULSE VARPULSE STRT CE TEST MODE LCD DISPLAY DRIVER MEMORY SHARE 1000-11FF RTM_0..
PAGE 56
71M6521DE/DH/FE Data Sheet System Power (V3P3SYS) V1_OK Battery Current MPU Mode 300nA BROWNOUT PLL_OK MISSION 13..14 CK cycles WAKE MPU Clock Source Transition PLL (4.2MHz/MUX_DIV) Xtal 2048...4096 CK32 cycles time Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ 300nA BROWNOUT Xtal MISSION PLL (4.2MHz) 14.
PAGE 57
71M6521DE/DH/FE Data Sheet VBAT Battery Current BROWNOUT MPU Mode MPU Clock Source WAKE Xtal 14.5 CK32 cycles PLL_OK Internal RESETZ 1024 CK32 cycles VBAT_OK time Figure 24: Power-Up Timing with VBAT only Fault and Reset Behavior Reset Mode: When the RESET pin is pulled high all digital activity stops. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are set to their default states.
PAGE 58
71M6521DE/DH/FE Data Sheet Wake on PB If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally pulled to GND and can be pulled high by a push button depression. Before the PB signal rises, the MPU is in reset due to the internal signal WAKE being low. When PB rises, WAKE rises and within three crystal cycles, the MPU begins to execute. The MPU can determine whether the PB signal woke it up by checking the IE_PB flag.
PAGE 59
71M6521DE/DH/FE Data Sheet Data Flow The data flow between CE and MPU is shown in Figure 26. In a typical application, the 32-bit compute engine (CE) sequentially processes the samples from the voltage inputs on pins IA, VA, IB, and VB, performing calculations to measure active power (Wh), reactive power (VARh), A2h, and V2h for four-quadrant metering. These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU.
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71M6521DE/DH/FE Data Sheet APPLICATION INFORMATION Connection of Sensors (CT, Resistive Shunt) Figure 28 and Figure 29 show how resistive dividers, current transformers, and restive shunts are connected to the voltage and current inputs of the 71M6521DE/DH/FE.
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71M6521DE/DH/FE Data Sheet Temperature Measurement Measurement of absolute temperature uses the on-chip temperature sensor while applying the following formula: T= ( N (T ) − N n ) + Tn Sn In the above formula T is the temperature in °C, N(T) is the ADC count at temperature T, Nn is the ADC count at 25°C, Sn is the sensitivity in LSB/°C as stated in the Electrical Specifications, and Tn is +25°C.
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71M6521DE/DH/FE Data Sheet Condition Parameter Min VREF(T) deviation from VNOM(T) VREF (T ) − VNOM (T ) 10 6 VNOM (T ) max( T − 22 ,40) Typ -20 +20 PPM/ºC Table 62: VREF Definition for the High-Accuracy Parts Figure 30 and Figure 31 show this concept graphically. The “box” from -18°C to +62°C reflects the fact that it is impractical to measure the temperature coefficient of high-quality references at small temperature excursions.
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71M6521DE/DH/FE Data Sheet Error Band (PPM) over Temperature (°C) 1400 ±20 PPM/°C 1000 600 200 -200 -600 -1000 ±20 PPM/°C -1400 -40 -20 0 20 40 60 80 Figure 31: Error Band for VREF over Temperature (High-Accuracy Parts) Temperature Compensation: The CE provides the bandgap temperature to the MPU, which then may digitally compensate the power outputs for the temperature dependence of VREF, using the CE register GAIN_ADJ.
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71M6521DE/DH/FE Data Sheet Temperature Compensation and Mains Frequency Stabilization for the RTC The flexibility provided by the MPU allows for compensation of the RTC using the substrate temperature. To achieve this, the crystal has to be characterized over temperature and the three coefficients Y_CAL, Y_CALC, and Y_CAL_C2 have to be calculated.
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71M6521DE/DH/FE Data Sheet 32768.5 32768.4 32768.3 32768.2 32768.1 32768 32767.9 32767.8 crystal 32767.7 curve fit 32767.6 inverse curve 32767.5 -50 -25 0 25 50 Figure 33: Crystal Compensation The MPU Demo Code supplied with the Teridian Demo Kits has a direct interface for these coefficients and it directly controls the RTC_DEC_SEC or RTC_INC_SEC registers.
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71M6521DE/DH/FE Data Sheet Connecting LCDs The 71M6521DE/DH/FE has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 34 shows the basic connection for a LCD. 6521 LCD segments commons Figure 34: Connecting LCDs The LCD segment pins can be organized in the following groups: 1. Nineteen pins are dedicated LCD segment pins (SEG0 to SEG18). 2. Four pins are dual-function pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32. 3.
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71M6521DE/DH/FE Data Sheet LCD_NUM SEG in Addition to SEG0-SEG18 Total Number of LCD Segment Pins Including SEG0SEG18 DIO Pins in Addition to DIO1-DIO2 Total Number of DIO Pins Including DIO1, DIO2 0 None 19 4-11,14-17, 19-21 18 1 41 20 4-11, 14-17, 19-20 17 2 40-41 21 4-11, 14-17, 19 16 3 39-41 22 4-11, 14-17 15 4 39-41 22 4-11, 14-17 15 5 37, 39-41 23 4-11, 14-16 14 6 36-37, 39-41 24 4-11, 14-15 13 7 35-37, 39-41 25 4-11, 14 12 8 34-37, 39-41 26 4-11 11 9
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71M6521DE/DH/FE Data Sheet LCD_NUM SEG in Addition to SEG0-SEG18 Total Number of LCD Segment Pins Including SEG0-SEG18 DIO Pins in Addition to DIO1-DIO2 Total Number of DIO Pins Including DIO1, DIO2 0 - 19 4-11, 14-17 14 1 - 19 4-11, 14-17 14 2 - 19 4-11, 14-17 14 3 - 19 4-11, 14-17 14 4 - 19 4-11, 14-17 14 5 37 20 4-11, 14-16 13 6 36-37 21 4-11, 14-15 12 7 35-37 22 4-11, 14 11 8 34-37 23 4-11 10 9 34-37 23 4-11 10 10 34-37 23 4-11 10 11 31, 34-3
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71M6521DE/DH/FE Data Sheet Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 36. DIO5 connects to both the DI and DO pins of the three-wire device. The CS pin must be connected to a vacant DIO pin of the 71M6521DE/DH/FE.
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71M6521DE/DH/FE Data Sheet Optical Interface The pins OPT_TX and OPT_RX can be used for a regular serial interface, e.g. by connecting a RS_232 transceiver, or they can be used to directly operate optical components, e.g. an infrared diode and phototransistor implementing a FLAG interface. Figure 38 shows the basic connections. The OPT_TX pin becomes active when the I/O RAM register OPT_TXDIS is set to 0.
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M6521DE/DH/FE Data Sheet Even though a functional meter will not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping, as shown in Figure 40, left side. The RESET signal may be sourced from V3P3SYS (functional in MISSION mode only), V3P3D (MISSION and BROWNOUT modes), VBAT (all modes, if battery is present), or from a combination of these sources, depending on the application.
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71M6521DE/DH/FE Data Sheet Crystal Oscillator The oscillator of the 71M6521DE/DH/FE drives a standard 32.768kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. Board layouts with minimum capacitance from XIN to XOUT will require less battery current.
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71M6521DE/DH/FE Data Sheet FIRMWARE INTERFACE I/O RAM MAP – In Numerical Order ‘Not Used’ bits are grayed out, contain no memory and are read by the MPU as zero. RESERVED bits may be in use and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers.
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71M6521DE/DH/FE Data Sheet RTM Probes: RTM0 2060 RTM1 2061 RTM2 2062 RTM3 2063 Pulse Generator: PLS_W 2080 PLS_I 2081 RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] SFR MAP (SFRs Specific to the Teridian 80515) – In Numerical Order ‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and should not be changed.
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71M6521DE/DH/FE Data Sheet I/O RAM DESCRIPTION – Alphabetical Order Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address range 0x2xxx. Bits with R (read) direction can be read by the MPU.
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71M6521DE/DH/FE Data Sheet DIO_DIR1[7:6, 3:0] SFR91 [7:6,3:0] 0 0 R/W Programs the direction of pins DIO15-DIO14, DIO11-DIO8. 1 indicates output. Ignored if the pin is not configured as I/O.
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71M6521DE/DH/FE Data Sheet FLSH_ERASE[7:0] SFR94[7:0] 0 0 W FLSH_MEEN SFRB2[1] 0 0 W FLSH_PGADR[6:0] SFRB7[7:1] 0 0 W FLSH_PWE SFRB2[0] 0 0 R/W FOVRIDE 20FD[4] 0 0 R/W IE_FWCOL0 IE_FWCOL1 IE_PB SFRE8[2] SFRE8[3] SFRE8[4] 0 0 0 0 0 -- R/W R/W R/W IE_PLLRISE SFRE8[6] 0 0 R/W IE_PLLFALL SFRE8[7] 0 0 R/W IE_XFER IE_RTC SFRE8[0] SFRE8[1] 0 0 0 0 R/W IE_WAKE SFRE8[5] 0 -- R/W INTBITS SFRF8[6:0] -- -- R/W LCD_BLKMAP19[3:0] LCD_BLKMAP18[3:0] 205A[7:4] 205A[3:0
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71M6521DE/DH/FE Data Sheet LCD_E 2021[5] 0 -- R/W LCD_MODE[2:0] 2021[4:2] 0 -- R/W LCD_NUM[4:0] 2020[4:0] 0 -- R/W LCD_ONLY 20A9[5] 0 0 W LCD_SEG0[3:0] … LCD_SEG19[3:0] LCD_SEG24[3:0] … LCD_SEG38[3:0] 2030[3:0] … 2043[3:0] 2048[3:0] … 2056[3:0] 0 … 0 0 … 0 -… --… -- R/W LCD_Y 2021[6] 0 0 R/W MPU_DIV[2:0] 2004[2:0] 0 0 R/W MUX_ALT 2005[2] 0 0 R/W Page: 78 of 107 R/W Enables the LCD display.
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71M6521DE/DH/FE Data Sheet MUX_DIV[1:0] OPT_FDC[1:0] 2002[7:6] 2007[1:0] 0 0 0 0 R/W The number of states in the input multiplexer.
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71M6521DE/DH/FE Data Sheet RTC_DEC_SEC RTC_INC_SEC 201C[1] 201C[0] 0 0 0 0 W RTM_E 2002[3] 0 0 R/W 2060 2061 2062 2063 SFRB2[6] 0 0 0 0 0 0 0 0 0 -- R/W 20A9[6] 0 0 W 2001[5:0] 20AA[4:0] 0 2 0 -- R/W R/W 20FF 0 0 R/W RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] SECURE SLEEP SUM_CYCLES[5:0] TMUX[4:0] TRIM[7:0] TRIMSEL[3:0] Page: 80 of 107 20FD[3:0] 0 0 R/W R/W RTC time correction bits. Only one bit may be pulsed at a time.
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71M6521DE/DH/FE Data Sheet VERSION[7:0] 2006 -- -- R VREF_CAL 2004[7] 0 0 R/W VREF_DIS WAKE_ARM 2004[3] 20A9[7] 0 0 1 -- R/W W WAKE_PRD 20A9[2:0] 001 -- R/W WAKE_RES 20A9[3] 0 -- R/W WD_RST SFRE8[7] 0 0 W WD_OVF 2002[2] 0 0 R/W 201F7:0] -- -- W WE Rev 3 The version index. This word may be read by firmware to determine the silicon version. VERSION[7:0] Silicon Version 0000 0110 A06 Brings VREF to VREF pad. This feature is disabled when VREF_DIS=1.
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71M6521DE/DH/FE Data Sheet CE Interface Description CE Program The CE program is supplied as a data image that can be merged with the MPU operational code for meter applications. Typically, the CE program covers most applications and does not need to be modified. For EQU = 0 and EQU = 1, CE code CE21A04_2 should be used. For EQU = 2, CE code image CE21A03_2 should be used. The description in this section applies to CE code revision CE21A03_2. Formats All CE words are 4 bytes.
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71M6521DE/DH/FE Data Sheet During operation, the MPU is in charge of controlling the multiplexer cycles, for example by inserting an alternate multiplexer sequence at regular intervals using MUX_ALT. This enables temperature measurement. The polarity of chopping circuitry must be altered for each sample. It must also alternate for each alternate multiplexer reading. This is accomplished by maintaining CHOP_E = 00.
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71M6521DE/DH/FE Data Sheet The significance of the bits in CESTATUS is shown in the table below: CESTATUS [bit] Name 31-29 Not Used 28 F0 27 RESERVED 26 SAG_B Normally zero. Becomes one when VB remains below SAG_THR for SAG_CNT samples. Will not return to zero until VB rises above SAG_THR. 25 SAG_A Normally zero. Becomes one when VA remains below SAG_THR for SAG_CNT samples. Will not return to zero until VA rises above SAG_THR. 24-0 Not Used Description These unused bits will always be zero.
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71M6521DE/DH/FE Data Sheet CECONFIG [bit] Name [15:8] Default Description SAG_CNT 80 (0x50) Number of consecutive voltage samples below SAG_THR before a sag alarm is declared. The maximum value is 255. SAG_THR is at address 0x14. [7] -- 0 Unused [6] FREQSEL 0 Selected phase for frequency monitor (0 = A, 1 = B). [5] EXT_PULSE 1 When zero, causes the pulse generators to respond to WSUM_X and VARSUM_X. Otherwise, the generators respond to values the MPU places in APULSEW and APULSER.
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71M6521DE/DH/FE Data Sheet Fundamental Energy Measurement Variables The table below describes each transfer variable for fundamental energy measurement. All variables are signed 32 bit integers. Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the integration time is 1 second. Additionally, the hardware will not permit output values to ‘fold back’ upon overflow.
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71M6521DE/DH/FE Data Sheet CE Address Name Default 0x7C MAINEDGE_X N/A The number of zero crossings of the selected voltage in the previous accumulation interval. Zero crossings are either direction and are debounced. 0x7B TEMP_RAW_X N/A Filtered, unscaled reading from the temperature sensor. 0x12 GAIN_ADJ 16384 Scales all voltage and current inputs. 16384 provides unity gain. 0x14 SAG_THR 443000 The threshold for sag warnings. The default value is equivalent to 80V RMS -7 if VMAX = 600V.
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71M6521DE/DH/FE Data Sheet CE Calibration Parameters The table below lists the parameters that are typically entered to effect calibration of meter accuracy. CE Address Name Default 0x08 CAL_IA 16384 0x09 CAL_VA 16384 0x0A CAL_IB 16384 0x0B CAL_VB 16384 PHADJ_A 0x0C Description These constants control the gain of their respective channels. The nominal value for each parameters is 214 = 16384. The gain of each channel is directly proportional to its CAL parameter.
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71M6521DE/DH/FE Data Sheet ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supplies and Ground Pins: V3P3SYS, V3P3A VBAT GNDD Analog Output Pins: −0.5 V to 4.6 V -0.5 V to 4.6 V -0.5 V to +0.5 V V3P3D -10 mA to 10 mA, -0.5 V to 4.6 V VREF -10 mA to +10 mA, -0.5 V to V3P3A+0.5 V V2P5 -10 mA to +10 mA, -0.5 V to 3.0V Analog Input Pins: IA, VA, IB, VB, V1 -10 mA to +10 mA -0.5 V to V3P3A+0.5 V XIN, XOUT -10 mA to +10 mA -0.5 V to 3.
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71M6521DE/DH/FE Data Sheet RECOMMENDED EXTERNAL COMPONENTS NAME C1 C2 CSYS C2P5 FROM V3P3A V3P3D V3P3SYS V2P5 TO AGND DGND DGND DGND XTAL XIN XOUT CXS † XIN AGND XOUT AGND CXL † FUNCTION Bypass capacitor for 3.3 V supply Bypass capacitor for 3.3 V output Bypass capacitor for V3P3SYS Bypass capacitor for V2P5 32.768 kHz crystal – electrically similar to ECS .327-12.5-17X or Vishay XT26T, load capacitance 12.
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71M6521DE/DH/FE Data Sheet PERFORMANCE SPECIFICATIONS INPUT LOGIC LEVELS PARAMETER Digital high-level input voltage†, VIH Digital low-level input voltage†, VIL Input pull-up current, IIL E_RXTX, E_RST, CKTEST Other digital inputs Input pull down current, IIH ICE_E PB Other digital inputs † CONDITION VIN=0 V, ICE_E=1 VIN=V3P3D MIN 2 TYP MAX 0.8 UNIT V V µA µA µA µA µA µA 10 10 -1 0 100 100 1 10 -1 -1 0 0 100 1 1 In battery powered modes, digital inputs should be below 0.3V or above 2.
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71M6521DE/DH/FE Data Sheet SUPPLY CURRENT PARAMETER V3P3A + V3P3SYS current VBAT current CONDITION Normal Operation, V3P3A=V3P3SYS=3.3 V MPU_DIV=3 (614kHz) CKOUT_E=00, CE_EN=1, RTM_E=0, ECK_DIS=1, ADC_E=1, ICE_E=0 MIN TYP MAX UNIT 6.1 7.7 mA +300 nA -300 V3P3A + V3P3SYS current vs. MPU clock frequency Same conditions as above 0.5 V3P3A + V3P3SYS current, write flash Normal Operation as above, except write flash at maximum rate, CE_E=0, ADC_E=0 9.1 10 mA 48 651 120 1501 µA µA 5.7 8.
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71M6521DE/DH/FE Data Sheet CRYSTAL OSCILLATOR PARAMETER Maximum Output Power to Crystal XIN to XOUT Capacitance Capacitance to DGND XIN XOUT CONDITION Crystal connected MIN TYP 3 MAX 1 UNIT μW pF 5 5 VREF, VBIAS Unless otherwise specified, VREF_DIS=0 PARAMETER CONDITION VREF output voltage, VNOM(25) Ta = 22ºC VREF chop step VREF_CAL =1, VREF output impedance ILOAD = 10 µA, -10 µA MIN 1.193 TYP 1.195 pF pF MAX 1.197 50 UNIT V mV 2.
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71M6521DE/DH/FE Data Sheet LCD DRIVERS Applies to all COM and SEG pins. PARAMETER MIN CONDITION VLC2 Max Voltage With respect to VLCD -0.1 VLC1 Voltage, 1/3 bias With respect to 2*VLC2/3 -4 ½ bias With respect to VLC2/2 -3 VLC0 Voltage, 1/3 bias With respect to VLC2/3 -3 ½ bias With respect to VLC2/2 -3 VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes. TYP MAX +0.
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71M6521DE/DH/FE Data Sheet TEMPERATURE SENSOR PARAMETER Nominal Sensitivity (Sn) CONDITION † Nominal (Nn) † † Temperature Error†  ( N (T ) − N n )  + Tn  ERR = T −  Sn   MIN TA=25ºC, TA=75ºC, FIR_LEN = 1 Nominal relationship: N(T)= Sn*(T-Tn)+Nn TA = -40ºC to +85ºC Tn = 25°C -101 TYP MAX UNIT -2180 LSB/ºC 1.0 106 LSB +101 ºC 1 Guaranteed by design; not production tested. LSB values do not include the 9-bit left shift at CE input.
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71M6521DE/DH/FE Data Sheet TIMING SPECIFICATIONS RAM AND FLASH MEMORY PARAMETER CE DRAM wait states Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations CONDITION CKMPU = 4.9 MHz CKMPU = 1.
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71M6521DE/DH/FE Data Sheet TYPICAL PERFORMANCE DATA 0.5 0.4 0.3 Error [%] 0.2 0.1 0 -0.1 -0.2 Phase_0 -0.3 Phase_60 -0.4 Phase_300 -0.5 0.1 1 10 100 1000 Current [A] Figure 42: Wh Accuracy, 0.1A to 200A at 240V/50Hz and Room Temperature 2 1 0 Error [%] -1 -2 -3 50Hz Harmonic Data 60Hz Harmonic Data -4 -5 -6 -7 -8 1 3 5 7 9 11 13 15 17 19 21 23 25 Harmonic Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%.
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71M6521DE/DH/FE Data Sheet Relative Accuracy over Temperature Accuracy [PPM/°C] 40 30 20 10 0 -10 -20 -30 -60 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 44: Typical Meter Accuracy over Temperature Relative to 25°C (71M6521FE) PACKAGE OUTLINE (LQFP 64) 11.7 12.3 11.7 + 12.3 PIN No. 1 Indicator 9.8 10.2 0.60 Typ. 0.50 Typ. 0.00 0.20 0.14 0.28 1.40 1.
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71M6521DE/DH/FE Data Sheet PACKAGE OUTLINE (QFN 68) Dimensions (in mm): Symbol Min. Nom. Max. Comment Pin pitch (CC) e 0.4 BSC Nd 17 Pins per row Ne 17 Pins column A 0.85 0.90 0.01 0.05 A2 0.65 0.70 A3 0.20 REF A1 b 0.00 0.15 0.20 D 8.00 BSC D1 7.75 BSC D2 6.3 E 8.00 BSC E1 7.75 BSC E2 0.25 Total height Pin width *) Total width Exposed pad **) Total length 6.3 Exposed pad b 0.15 0.20 0.25 Pad width P 0.24 0.42 0.
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71M6521DE/DH/FE Data Sheet IA VB VA V3P3A GNDA 52 51 50 49 55 IB VREF 56 53 V1 57 54 X4MHZ OPT_RX/DIO1 58 TEST XIN 59 61 60 PB XOUT 62 E_TCLK/SEG33 E_RST/SEG32 64 63 PINOUT (LQFP-64) GNDD 1 E_RXTX/SEG38 2 OPT_TX/DIO2 3 TMUXOUT 4 TX 5 SEG3 6 43 SEG30/DIO10 V3P3D 7 42 SEG29/DIO9 CKTEST/SEG19 8 41 SEG28/DIO8 V3P3SYS 9 40 SEG27/DIO7 ° 48 TERIDIAN 71M6521FE-IGT RESET 47 V2P5 46 VBAT 45 RX 44 SEG31/DIO11 39 SEG26/DIO6 38 SEG25/DIO5 SEG4
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71M6521DE/DH/FE Data Sheet Recommended PCB Land Pattern for the QFN-68 Package Recommended PCB Land Pattern Dimensions Symbol Description Typical Dimension e Lead pitch 0.4mm x Pad width 0.23mm y Pad length, see note 3 0.8mm d See note 1 6.3mm A 6.63mm G 7.2mm Note 1: Do not place unmasked vias in region denoted by dimension “d”. Note 2: Soldering of bottom internal pad is not required for proper operation.
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71M6521DE/DH/FE Data Sheet PIN DESCRIPTIONS Power/Ground Pins: Name Type Circuit Description GNDA P -- Analog ground: This pin should be connected directly to the ground plane. GNDD P -- V3P3A P -- V3P3SYS P -- V3P3D O 13 VBAT P 12 V2P5 O 10 Digital ground: This pin should be connected directly to the ground plane. Analog power supply: A 3.3V power supply should be connected to this pin, must be the same voltage as V3P3SYS. System 3.3V supply. This pin should be connected to a 3.
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71M6521DE/DH/FE Data Sheet Digital Pins: Name Type Circuit O 5 O 5 I/O 3, 4, 5 I/O 3, 4, 5 I/O 3, 4, 5 I/O 1, 4, 5 O 4, 5 ICE_E I 2 CKTEST/SEG19 O 4, 5 TMUXOUT O 4 OPT_RX/DIO1 I/O 3, 4, 7 OPT_TX/DIO2 I/O 3, 4 DIO3 I/O 3, 4 RESET I 3 RX I 3 TX O 4 UART output. TEST I 7 PB I 3 X4MHZ I 3 Enables Production Test. Must be grounded in normal operation. Push button input.
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71M6521DE/DH/FE Data Sheet I/O Equivalent Circuits: V3P3D V3P3D V3P3A 110K Digital Input Pin CMOS Input LCD SEG Output Pin LCD Driver GNDD from internal reference VREF Pin GNDA GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D VREF Equivalent Circuit Type 9: VREF LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG V3P3A V3P3D Digital Input Pin CMOS Input 110K GNDD GNDD Analog Input Pin fro
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71M6521DE/DH/FE Data Sheet ORDERING INFORMATION PART DESCRIPTION (Package) Accuracy (ppm/°C) FLASH MEMORY SIZE (KB) PACKAGIN G 71M6521DE 64-pin LQFP, lead(Pb)-free ±40 16 Bulk 71M6521DE 64-pin LQFP, lead(Pb)-free ±40 16 Tape & Reel 71M6521DH* 64-pin LQFP, lead(Pb)-free ±20 16 Bulk 71M6521DH* 64-pin LQFP, lead(Pb)-free ±20 16 Tape & Reel 71M6521FE 64-pin LQFP, lead(Pb)-free ±40 32 Bulk 71M6521FE 64-pin LQFP, lead(Pb)-free ±40 32 Tape & Reel 71M6521DE 68-pin QFN, lead(Pb)-f
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71M6521DE/DH/FE Data Sheet REVISION HISTORY REVISION NUMBER REVISION DATE 1.1 2 10/10 11/11 DESCRIPTION Added the note “Guaranteed by design; not production tested.
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71M6521DE/DH/FE Data Sheet Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000  2012 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.