Datasheet

FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 115
5.9.3 Digital Pins
Table 92: Digital Pins
Name
Type
Circuit
Description
COM3,COM2,
COM1,COM0
O 5
LCD Common Outputs: These 4 pins provide the select signals for
the LCD display.
SEG0…SEG2,
SEG7, SEG8
SEG12…SEG18
O 5
Dedicated LCD Segment Output pins.
SEG20…SEG23
O
5
Dedicated LCD Segment Output pins (71M6532D/F only).
SEG24/DIO4…
SEG35/DIO15,
SEG37/DIO17,
SEG48/DIO28,
SEG49/DIO29,
SEG63/DIO43…
SEG66/DIO46
I/O 3, 4, 5
Multi-use pins, configurable as either LCD SEG driver or DIO.
(DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface;
WPULSE = DIO6, VARPULSE = DIO7 when configured as pulse
outputs). Unused pins must be configured as outputs or terminated
to V3P3/GNDD.
1)
SEG3/PCLK
SEG4/PSDO
SEG5/PCSZ
SEG6/PSDI
I/O 3, 4, 5
Multi-use pins, configurable as either LCD SEG driver or SPI PORT.
E_RXTX/SEG9
I/O
1, 4, 5
Multi-use pins, configurable as either emulator port pins (when ICE_E
pulled high) or LCD SEG drivers (when ICE_E tied to GND).
E_RST/SEG11
I/O
1, 4, 5
E_TCLK/SEG10
O
4, 5
ICE_E I 2
ICE enable. When zero, E_RST, E_TCLK and E_RXTX become
SEG32, SEG33 and SEG38 respectively. For production units, this
pin should be pulled to GND to disable the emulator port.
CKTEST/SEG19,
MUXSYNC/SEG7
O 4, 5
Multi-use pins, configurable as either multiplexer/clock output or LCD
segment driver using the I/O RAM registers CKOUT_E or
MUX_SYNC_E.
TMUXOUT
O
4
Digital output test multiplexer. Controlled by TMUX[3:0].
OPT_RX/DIO1 I/O 3, 4, 7
Multi-use pin, configurable as Optical Receive Input or general DIO.
When configured as OPT_RX, this pin receives a signal from an external
photo-detector used in an IR serial interface. If this pin is unused it
must be configured as an output or terminated to V3P3D or GNDD.
OPT_TX/DIO2 I/O 3, 4
Multi-use pin, configurable as either optical LED transmit output,
WPULSE, RPULSE, or general DIO. When configured as OPT_TX,
this pin is capable of directly driving an LED for transmitting data in
an IR serial interface.
RESET I 2
Chip reset: This input pin is used to reset the chip into a known state.
For normal operation, this pin is pulled low. To reset the chip, this pin
should be pulled high. This pin has an internal 30 μA (nominal) current
source pull-down. No external reset circuitry is necessary.
RX I 3
UART input. If this pin is unused it must be configured as an
output or terminated to V3P3D or GNDD.
TX
O
4
UART output.
TEST I 7
Enables Production Test. This pin must be grounded in normal
operation.
PB I 3
Push button input. This pin must be at GNDD when not active. A
rising edge sets the IE_PB flag. It also causes the part to wake up if it
is in SLEEP or LCD mode. PB does not have an internal pull-up or
pull-down.
1)
Not all pins available on the 71M6531D/F or 71M6532D/F.