Datasheet

Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
120 Rev 2
access via the SPI interface. Added Table 50.
9) 2.3 Battery Modes (page 56, 57): Added details on software pre-
cautions for switching between modes and factory programming of
the first 6 flash addresses.
10) 3.1 Connection of Sensors (page 63): Added note concerning
analog input pins requiring sensors with low source impedance.
11) 3.15 MPU Firmware (page 70): Modified to indicate demonstration
source code provided.
12) 3.16 Crystal Oscillator (page 70): Updated caution concerning
rejecting electromagnetic interference.
13) Table 54: I/O RAM Map in Functional Order (page 72): Updated
Unused and NVRAM locations.
14) 4.3.4 Environment: Added comment concerning importance of
parameter dependence on CE code environment.
15) 4.3.6 CE Status and Control (page 89):
 Updated description of F0 in Table 57.
 Updated descriptions in Table 58 (page 91).
16) 4.3.7 CE Transfer Variables: Updated description of
VBAT_SUM_X in Table 63 (page 93).
17) Corrected values for EXT_PULSE in description of internal pulse
generation (page 89).
18) Updated pin-out for QFN-68 package (Figure 48).
19) Added explanation for InSQRES_X.
20) Added explanation of delay compensation in CE (1.3.5).
21) Added explanation on temperature coefficients for VERF in Appli-
cation Section (3.4.1).
22) Corrected Figure 30 (right side).
1.2
October 21, 2009
Updated number range for RTC_ADJ to 0 – 0x7F and tolerance for ex-
posed pad in Figure 46 to 0.1 mm. Corrected bit range for CE_LCTN
to [7:0] and functional description for TMOD[7] and TMOD[3] in Table
22. Added maximum value for WRATE and text stating that registers
RTC_SEC to RTC_YR do not change at reset. Added V LSB entry for
sag detection in CE Interface Description, text regarding hysteresis at
section 3.10, note that VX pin is not supported by standard CE code,
and description of STOP and IDLE bits in PCON register. Changed
value for Wh accuracy percentage on title page (value stated for
room temperature).
1.1
July 27, 2009
Updated mechanical drawing for QFN-68 package.
Replaced Figure 19 with single-phase example.
Corrected LQFP-100 package drawing (Figure 50).
Applied minor corrections and enhancements to diagrams.
1.0
February 27,
2009
Initial release. Changes with respect to PDS v1.3:
1) Corrected Timer/Counter 0/1 label in Table 22.
2) Corrected entries for DIO29 and DIO43 in Table 39.
3) Updated unused/reserved bits in I/O RAM tables, added descrip-
tion for WE register.
4) Documented blink capability for both SEG18 and SEG19.
5) Changed package for 71M6532D/F to LQFP-100, updated all pin
tables and I/O RAM tables accordingly.
6) Replaced graph showing system performance specification over
temperature with specification on accuracy of VREF compensa-
tion.
7) Added explanation for hysteresis at the V1 pin in Applications
Section.
8) Added note on recommended bypass capacitors C1 and C2 in
Electrical Specification.