Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
![](/manual/maxim-integrated/71m6531f-im-f/datasheet-english/images/img-16.png)
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
16 Rev 2
1.3.1 Meter Equations
The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE in order to support various
meter equations. This assistance is controlled through I/O RAM location EQU[2:0] (equation assist). The
Compute Engine (CE) firmware for residential configurations implements the equations listed in Table 5.
EQU[2:0] specifies the equation to be used based on the number of phases used for metering.
Table 5: Meter Equations
EQU[2:0]
Description
Watt and VAR Formula
Mux
Sequence
ALT Mux
Sequence
Element
0
Element
1
Element
2
0
1 element, 2 W,
1φ with neutral
current sense
VA ∙ IA VA ∙ IB N/A
Sequence is
programmable
with
SLOTn_SEL[3:0]
Sequence is
programmable with
SLOTn_ALTSEL[3:0]
1
1 element, 3 W,
1
φ
VA(IA-
IB)/2
N/A N/A
2
2 element, 3 W,
3φ Delta
VA ∙ IA VB ∙ IB N/A
Not all CE codes support all equations.
1.3.2 Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled
with the RTM_E bit. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output
enabled by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag
bit. See Figure 20 for the RTM output format. RTM is low when not in use.
1.3.3 Pulse Generators
The 71M6531D/F and 71M6532D/F provide four pulse generators, RPULSE, WPULSE, XPULSE and
YPULSE, as well as increased hardware support for the two original pulse generators (RPULSE and
WPULSE). The pulse generators can be used to output CE status indicators, SAG for example, to DIO pins.
The polarity of the pulses may be inverted with the PLS_INV bit. When this bit is set, the pulses are active
high, rather than the more usual active low. PLS_INV inverts all the pulse outputs.
XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8
and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on
each pass of the CE code, resulting in a pulse frequency up to a maximum of 1260Hz (assuming a MUX
frame is 13 CK32 cycles).
The YPULSE pin can be used by the CE code to generate interrupts based on sag events. This method
is faster than checking the sag bits by the MPU at every CE_BUSY interrupt. See Section 4.3.6 CE Status
and Control for details.
RPULSE and WPULSE
During each CE code pass, the hardware stores exported WPULSE AND RPULSE sign bits in an 8-bit
FIFO and outputs them at a specified interval. This permits the CE code to calculate the RPULSE and
WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX
frame. The FIFO is reset at the beginning of each MUX frame. The PLS_INTERVAL register controls the
delay to the first pulse update and the interval between subsequent updates. Its LSB is 4 CK_FIR cycles.
If zero, the FIFO is deactivated and the DFFs are updated immediately. Thus, N
INTERVAL is
4 * PLS_INTERVAL.