Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 29
Table 21: Allowed Timer/Counter Mode Combinations
Timer 1
Mode 0
Mode 1
Mode 2
Timer 0 - mode 0
Yes
Yes
Yes
Timer 0 - mode 1
Yes
Yes
Yes
Timer 0 - mode 2
Not allowed
Not allowed
Yes
Table 22: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol
Function
Timer/Counter 1:
TMOD[7] Gate
If TMOD[7] is set, external input signal control is enabled for Counter 0.
external gate control. The TR1 bit in the TCON register (SFR 0x88) must
also be set in order for Counter 1 to increment.
With these settings Counter 1 is incremented on every falling edge of the
logic signal applied to one or more of the interrupt sources controlled by
the DI_RBP, DIO_R1, … DIO_RXX registers.
TMOD[6] C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as a
timer.
TMOD[5:4]
M1:M0
Selects the mode for Timer/Counter 1 as shown in Table 20.
Timer/Counter 0:
TMOD[3] Gate
If TMOD[3] is set, external input signal control is enabled for Counter 0.
external gate control. The TR0 bit in the TCON register (SFR 0x88) must
also be set in order for Counter 0 to increment.
With these settings Counter 0 is incremented on every falling edge of the
logic signal applied to one or more of the interrupt sources controlled by
the DI_RBP, DIO_R1, … DIO_RXX registers.
TMOD[2] C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as
a timer.
TMOD[1:0]
M1:M0
Selects the mode for Timer/Counter 0, as shown in Table 20.
Table 23: The TCON Register Bit Functions (SFR 0x88)
Bit
Symbol
Function
TCON[7] TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when an
interrupt is processed.
TCON[6]
TR1
Timer 1 run control bit. If cleared, Timer 1 stops.
TCON[5] TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt
is processed.
TCON[4]
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON[3] IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external
pin int1 is observed. Cleared when an interrupt is processed.
TCON[2] IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on
input pin to cause an interrupt.
TCON[1] IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external
pin int0 is observed. Cleared when an interrupt is processed.
TCON[0] IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on
input pin to cause interrupt.